> Not exactly. There're an interrupt state name "RD_REQ" but no one named
> like "WR_REQ".
> 
> For read-request, the slave will get a RD_REQ interrupt. 
> For write-request, the slave won't be interrupted until data arrived to
> trigger interrupt "RX_FULL".
> 
> I tried to use GPIO to simulate an I2C master. I only sent its own
> address + W bit without any data and then I got only a STOP_DET interrupt.
> If I sent its own address + W bit + one byte data and then I got one
> RX_FULL and a STOP_DET.
> 
> It seems the controller doesn't interrupt when RW bit is W, but R does.

Thanks for the detailed explanation! Okay, then what you do looks
correct to me (from a high level perspective without really knowing the
HW): when RX is full, you first send the state WRITE_REQUESTED when
there is no other transfer on-going. Then you send WRITE_RECEIVED
immediately. I think this is the way to do it.