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[209.85.217.44]) by smtp.gmail.com with ESMTPSA id 89sm119280uaq.9.2020.10.13.14.35.54 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Oct 2020 14:35:54 -0700 (PDT) Received: by mail-vs1-f44.google.com with SMTP id v23so893930vsp.6 for ; Tue, 13 Oct 2020 14:35:54 -0700 (PDT) X-Received: by 2002:a67:eb52:: with SMTP id x18mr1584898vso.34.1602624953624; Tue, 13 Oct 2020 14:35:53 -0700 (PDT) MIME-Version: 1.0 References: <20201008225235.2035820-1-dianders@chromium.org> <20201008155154.1.Ifdb1b69fa3367b81118e16e9e4e63299980ca798@changeid> <160229038385.310579.7502548054994849649@swboyd.mtv.corp.google.com> <2ccc26a0-5d54-e06c-5a73-7eb353c393d2@codeaurora.org> In-Reply-To: <2ccc26a0-5d54-e06c-5a73-7eb353c393d2@codeaurora.org> From: Doug Anderson Date: Tue, 13 Oct 2020 14:35:42 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/3] soc: qcom: geni: More properly switch to DMA mode To: Akash Asthana Cc: Stephen Boyd , Bjorn Andersson , Wolfram Sang , linux-arm-msm , linux-i2c@vger.kernel.org, Andy Gross , Girish Mahadevan , Karthikeyan Ramasubramanian , Mukesh Kumar Savaliya , LKML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Hi, On Mon, Oct 12, 2020 at 2:05 AM Akash Asthana wrote: > > Hi Stephen, > > > >> > >> static void geni_se_select_dma_mode(struct geni_se *se) > >> { > >> + u32 proto = geni_se_read_proto(se); > >> u32 val; > >> > >> geni_se_irq_clear(se); > >> > >> + val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); > >> + if (proto != GENI_SE_UART) { > > Not a problem with this patch but it would be great if there was a > > comment here (and probably in geni_se_select_fifo_mode() too) indicating > > why GENI_SE_UART is special. Is it because GENI_SE_UART doesn't use the > > main sequencer? I think that is the reason, but I forgot and reading > > this code doesn't tell me that. > > > > Splitting the driver in this way where the logic is in the geni wrapper > > and in the engine driver leads to this confusion. > > GENI_SE_UART uses main sequencer for TX and secondary for RX transfers > because it is asynchronous in nature. > > That's why RX related bits (M_RX_FIFO_WATERMARK_EN | > M_RX_FIFO_LAST_EN) are not enable in main sequencer for UART. > > (M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN) bits are controlled from UART > driver, it's gets enabled and disabled multiple times from start_tx > ,stop_tx respectively. For now I've "solved" this by adding some comments (in the 3rd patch) basically summarizing what Akash said. I didn't want to go further than that for now because it felt more important to get the i2c bug fixed sooner rather than later and re-organizing would be a big enough change that it'd probably need a few spins. Our bug trackers don't make it trivially easy to file a public bug tracking this and assign it to Qualcomm, but I've filed a bug asking folks at Qualcomm to help with re-organizing things after my patch series lands. This is internally tracked at Google as b:170766462 ("Rejigger geni_se_select_fifo_mode() / geni_se_select_dma_mode() to not manage interrupt enables"). -Doug