From: Wolfram Sang <wsa@kernel.org>
To: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
Cc: linux-i2c@vger.kernel.org, michal.simek@xilinx.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, git@xilinx.com
Subject: Re: [PATCH] i2c: cadence: Clear HOLD bit before xfer_size register rolls over
Date: Wed, 23 Jun 2021 18:18:51 +0200 [thread overview]
Message-ID: <YNNe63q2T/9ndSgg@kunai> (raw)
In-Reply-To: <1606203965-31595-1-git-send-email-raviteja.narayanam@xilinx.com>
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On Tue, Nov 24, 2020 at 01:16:05PM +0530, Raviteja Narayanam wrote:
> On Xilinx zynq SOC if the delay between address register write and
> control register write in cdns_mrecv function is more, the xfer size
> register rolls over and controller is stuck. This is an IP bug and
> is resolved in later versions of IP.
>
> To avoid this scenario, disable the interrupts on the current processor
> core between the two register writes and enable them later. This can
> help achieve the timing constraint.
>
> Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
Applied to for-next, thanks!
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prev parent reply other threads:[~2021-06-23 16:19 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-24 7:46 [PATCH] i2c: cadence: Clear HOLD bit before xfer_size register rolls over Raviteja Narayanam
2021-06-23 8:46 ` Michal Simek
2021-06-23 16:18 ` Wolfram Sang [this message]
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