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[109.252.192.57]) by smtp.googlemail.com with ESMTPSA id n133sm3079342lfd.152.2021.01.11.03.50.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Jan 2021 03:50:41 -0800 (PST) Subject: Re: [PATCH v1] i2c: tegra: Fix i2c_writesl() to use writel() instead of writesl() To: Sowjanya Komatineni , Thierry Reding Cc: jonathanh@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org References: <1603166634-13639-1-git-send-email-skomatineni@nvidia.com> <20201020074846.GA1877013@ulmo> <538d8436-260d-40a8-b0a3-a822a0f9c909@nvidia.com> From: Dmitry Osipenko Message-ID: Date: Mon, 11 Jan 2021 14:50:40 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.2 MIME-Version: 1.0 In-Reply-To: <538d8436-260d-40a8-b0a3-a822a0f9c909@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org 20.10.2020 19:37, Sowjanya Komatineni пишет: > > On 10/20/20 12:48 AM, Thierry Reding wrote: >> On Mon, Oct 19, 2020 at 09:03:54PM -0700, Sowjanya Komatineni wrote: >>> VI I2C don't have DMA support and uses PIO mode all the time. >>> >>> Current driver uses writesl() to fill TX FIFO based on available >>> empty slots and with this seeing strange silent hang during any I2C >>> register access after filling TX FIFO with 8 words. >>> >>> Using writel() followed by i2c_readl() in a loop to write all words >>> to TX FIFO instead of using writesl() helps for large transfers in >>> PIO mode. >>> >>> So, this patch updates i2c_writesl() API to use writel() in a loop >>> instead of writesl(). >>> >>> Signed-off-by: Sowjanya Komatineni >>> --- >>>   drivers/i2c/busses/i2c-tegra.c | 9 ++++++--- >>>   1 file changed, 6 insertions(+), 3 deletions(-) >>> >>> diff --git a/drivers/i2c/busses/i2c-tegra.c >>> b/drivers/i2c/busses/i2c-tegra.c >>> index 6f08c0c..274bf3a 100644 >>> --- a/drivers/i2c/busses/i2c-tegra.c >>> +++ b/drivers/i2c/busses/i2c-tegra.c >>> @@ -333,10 +333,13 @@ static u32 i2c_readl(struct tegra_i2c_dev >>> *i2c_dev, unsigned int reg) >>>       return readl_relaxed(i2c_dev->base + >>> tegra_i2c_reg_addr(i2c_dev, reg)); >>>   } >>>   -static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, >>> +static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, u32 *data, >>>               unsigned int reg, unsigned int len) >>>   { >>> -    writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, >>> len); >>> +    while (len--) { >>> +        writel(*data++, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, >>> reg)); >>> +        i2c_readl(i2c_dev, I2C_INT_STATUS); >>> +    } >>>   } >>>     static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, >>> @@ -811,7 +814,7 @@ static int tegra_i2c_fill_tx_fifo(struct >>> tegra_i2c_dev *i2c_dev) >>>           i2c_dev->msg_buf_remaining = buf_remaining; >>>           i2c_dev->msg_buf = buf + words_to_transfer * >>> BYTES_PER_FIFO_WORD; >>>   -        i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); >>> +        i2c_writesl(i2c_dev, (u32 *)buf, I2C_TX_FIFO, >>> words_to_transfer); >> I've thought a bit more about this and I wonder if we're simply reading >> out the wrong value for tx_fifo_avail and therefore end up overflowing >> the TX FIFO. Have you checked what the value is for tx_fifo_avail when >> this silent hang occurs? Given that this is specific to the VI I2C I'm >> wondering if this is perhaps a hardware bug where we read the wrong TX >> FIFO available count. >> >> Thierry > > Yes FIFO status shows all 8 slots available. Please explain how you checked that 8 slots are available, provide example code.