From: Qii Wang <qii.wang@mediatek.com>
To: <bbrezillon@kernel.org>
Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com,
leilk.liu@mediatek.com, gregkh@linuxfoundation.org,
xinping.qian@mediatek.com, linux-kernel@vger.kernel.org,
liguo.zhang@mediatek.com, linux-mediatek@lists.infradead.org,
qii.wang@mediatek.com, matthias.bgg@gmail.com,
linux-i3c@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/2] dt-bindings: i3c: Document MediaTek I3C master bindings
Date: Wed, 26 Jun 2019 13:36:27 +0800 [thread overview]
Message-ID: <1561527388-4829-2-git-send-email-qii.wang@mediatek.com> (raw)
In-Reply-To: <1561527388-4829-1-git-send-email-qii.wang@mediatek.com>
Document MediaTek I3C master DT bindings.
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
---
.../devicetree/bindings/i3c/mtk,i3c-master.txt | 47 ++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt
diff --git a/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt b/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt
new file mode 100644
index 0000000..3fd4f17
--- /dev/null
+++ b/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt
@@ -0,0 +1,47 @@
+Bindings for MediaTek I3C master block
+=====================================
+
+Required properties:
+--------------------
+- compatible: shall be "mediatek,i3c-master"
+- reg: physical base address of the controller and apdma base, length of
+ memory mapped region.
+- reg-names: should be "main" for controller and "dma" for apdma.
+- interrupts: interrupt number to the cpu.
+- clocks: clock name from clock manager.
+- clock-names: must include "main" and "dma".
+
+Mandatory properties defined by the generic binding (see
+Documentation/devicetree/bindings/i3c/i3c.txt for more details):
+
+- #address-cells: shall be set to 3
+- #size-cells: shall be set to 0
+
+Optional properties defined by the generic binding (see
+Documentation/devicetree/bindings/i3c/i3c.txt for more details):
+
+- i2c-scl-hz
+- i3c-scl-hz
+
+I3C device connected on the bus follow the generic description (see
+Documentation/devicetree/bindings/i3c/i3c.txt for more details).
+
+Example:
+
+ i3c0: i3c@1100d000 {
+ compatible = "mediatek,i3c-master";
+ reg = <0x1100d000 0x100>,
+ <0x11000300 0x80>;
+ reg-names = "main", "dma";
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&i3c0_ck>, <&ap_dma_ck>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-scl-hz = <100000>;
+
+ nunchuk: nunchuk@52 {
+ compatible = "nintendo,nunchuk";
+ reg = <0x52 0x80000010 0>;
+ };
+ };
--
1.7.9.5
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next prev parent reply other threads:[~2019-07-04 9:56 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-26 5:36 [PATCH v2 0/2] Add MediaTek I3C master controller driver Qii Wang
2019-06-26 5:36 ` Qii Wang [this message]
2019-06-26 16:23 ` [PATCH v2 1/2] dt-bindings: i3c: Document MediaTek I3C master bindings Boris Brezillon
2019-06-27 7:25 ` Qii Wang
2019-07-04 10:00 ` Boris Brezillon
2019-06-26 5:36 ` [PATCH v2 2/2] i3c: master: Add driver for MediaTek IP Qii Wang
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