From: Boris Brezillon <boris.brezillon@collabora.com>
To: Vitor Soares <Vitor.Soares@synopsys.com>
Cc: linux-i3c@lists.infradead.org, Joao.Pinto@synopsys.com
Subject: Re: [PATCH v4 0/3] Fix i2c and i3c scl rate according bus mode
Date: Thu, 20 Jun 2019 10:56:02 +0200 [thread overview]
Message-ID: <20190620105602.28b538ae@collabora.com> (raw)
In-Reply-To: <cover.1560968688.git.vitor.soares@synopsys.com>
On Wed, 19 Jun 2019 20:36:30 +0200
Vitor Soares <Vitor.Soares@synopsys.com> wrote:
> This patch series fix the i2c and i3c scl rate according the bus mode
> and LVR register. It also introduce the mixed limited bus for the
> cases where i2c devices doesn't have 50 ns filter but allow higher
> clock rate for i3c transfers.
> Please refer table 5 and 10 of i3c bus spec v1.0 for more detail.
>
> Please follow each patch commit message for more details and changes
> made in this version.
>
> Vitor Soares (3):
> i3c: fix i2c and i3c scl rate by bus mode
> i3c: add mixed limited bus mode
> i3c: dw: add limited bus mode support
Queued to i3c/next.
Thanks,
Boris
>
> drivers/i3c/master.c | 57 +++++++++++++++++++++++++++++---------
> drivers/i3c/master/dw-i3c-master.c | 1 +
> include/linux/i3c/master.h | 5 ++++
> 3 files changed, 50 insertions(+), 13 deletions(-)
>
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prev parent reply other threads:[~2019-06-20 8:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-19 18:36 [PATCH v4 0/3] Fix i2c and i3c scl rate according bus mode Vitor Soares
2019-06-19 18:36 ` [PATCH v4 1/3] i3c: fix i2c and i3c scl rate by " Vitor Soares
2019-06-19 18:36 ` [PATCH v4 2/3] i3c: add mixed limited " Vitor Soares
2019-06-19 18:36 ` [PATCH v4 3/3] i3c: dw: add limited bus mode support Vitor Soares
2019-06-20 8:56 ` Boris Brezillon [this message]
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