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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Alexandre Belloni <alexandre.belloni@bootlin.com>,
	linux-i3c@lists.infradead.org
Cc: devicetree@vger.kernel.org,
	Rajeev Huralikoppi <rajeev.huralikoppi@silvaco.com>,
	Nicolas Pitre <nico@fluxnic.net>,
	Rob Herring <robh+dt@kernel.org>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Conor Culhane <conor.culhane@silvaco.com>
Subject: [PATCH v3 2/4] dt-bindings: i3c: Describe Silvaco master binding
Date: Mon, 28 Dec 2020 17:11:05 +0100	[thread overview]
Message-ID: <20201228161107.11804-3-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20201228161107.11804-1-miquel.raynal@bootlin.com>

Silvaco provide a dual-role I3C master.

Description is rather simple: it needs a register mapping, three
clocks and an interrupt.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 .../bindings/i3c/silvaco,i3c-master.yaml      | 63 +++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml

diff --git a/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml
new file mode 100644
index 000000000000..509de48455b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Silvaco I3C master
+
+maintainers:
+  - Conor Culhane <conor.culhane@silvaco.com>
+
+properties:
+  compatible:
+    const: silvaco,i3c-master
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: pclk, the system clock
+      - description: fast_clk, for the bus
+      - description: slow_clk, for other events
+
+  clock-names:
+    minItems: 3
+    maxItems: 3
+
+  resets:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clock-names
+  - clocks
+  - "#address-cells"
+  - "#size-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    i3c-master@a0000000 {
+        compatible = "silvaco,i3c-master";
+        clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>;
+        clock-names = "pclk", "fast_clk", "slow_clk";
+        interrupt-parent = <&gic>;
+        interrupts = <0 89 4>;
+        reg = <0xa0000000 0x1000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+    };
-- 
2.20.1


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  parent reply	other threads:[~2020-12-28 16:11 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-28 16:11 [PATCH v3 0/4] Silvaco I3C master driver Miquel Raynal
2020-12-28 16:11 ` [PATCH v3 1/4] dt-bindings: Add vendor prefix for Silvaco Miquel Raynal
2020-12-28 16:11 ` Miquel Raynal [this message]
2021-01-11 20:08   ` [PATCH v3 2/4] dt-bindings: i3c: Describe Silvaco master binding Rob Herring
2021-01-14 17:55     ` Miquel Raynal
2020-12-28 16:11 ` [PATCH v3 3/4] i3c: master: svc: Add Silvaco I3C master driver Miquel Raynal
2020-12-28 16:11 ` [PATCH v3 4/4] MAINTAINERS: Add Silvaco I3C master Miquel Raynal

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