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Wed, 7 Apr 2021 23:00:24 +0000 Subject: Re: [PATCH v4 3/3] ata: ahci_tegra: Add AHCI support for Tegra186 From: Sowjanya Komatineni To: Dmitry Osipenko , , , , CC: , , , , References: <1617758731-12380-1-git-send-email-skomatineni@nvidia.com> <1617758731-12380-4-git-send-email-skomatineni@nvidia.com> <594c622e-4505-3448-1c7b-eae8f36cbad8@gmail.com> <49eba27e-18fa-b682-1385-2930dfff28ac@nvidia.com> Message-ID: <01fd01ab-f4e7-57ee-2ad7-2aabaeb92a0e@nvidia.com> Date: Wed, 7 Apr 2021 16:00:33 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <49eba27e-18fa-b682-1385-2930dfff28ac@nvidia.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ac8213d2-8264-478e-0036-08d8fa18ee27 X-MS-TrafficTypeDiagnostic: DM4PR12MB5295: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2021 23:00:25.3588 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac8213d2-8264-478e-0036-08d8fa18ee27 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5295 Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org On 4/7/21 3:57 PM, Sowjanya Komatineni wrote: > > On 4/7/21 2:36 PM, Dmitry Osipenko wrote: >> 07.04.2021 04:25, Sowjanya Komatineni пишет: >>> +    if (!tegra->pdev->dev.pm_domain) { >>> +        ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA, >>> +                            tegra->sata_clk, >>> +                            tegra->sata_rst); >>> +        if (ret) >>> +            goto disable_regulators; >>> +    } >> Hi, >> >> Why you haven't added condition for tegra_powergate_power_off()? I think >> it should break GENPD and legacy PD API isn't not supported by T186 >> at all. >> >> I'm also not sure whether the power up/down sequence is correct using >> GENPD. >> >> Moreover the driver doesn't support runtime PM, so GENPD should be >> always off? > > This driver already using legacy PD API's so thought its supported and > added power domain device check during powergate_sequence_power_up and > yes same should apply for powergate_power_off as well. But if legacy > PD is not supported by T186 then not sure why original driver even > using these API's. > > Sorry just took a look and driver supports T210 and prior tegra as well. T210 and prior supports legacy PD and this check is applicable for those. So we should add power domain device check for power off as well. But for T186, we should have GENPD working once we add runtime PM support to driver. Preetham/Thierry, Can you confirm where SATA is un powergated prior to kernel? > But as RPM is not implemented yet for this driver, GENPD will be OFF > but SATA is not in power-gate by the time kernel starts and > functionally works. > > But with RPM implementation, I guess we can do proper power gate on/off. >