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Tue, 22 Sep 2020 03:16:11 -0700 Received: from [10.140.6.6] (helo=xhdappanad40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1kKfLH-0001dQ-9j; Tue, 22 Sep 2020 03:16:11 -0700 From: Piyush Mehta To: axboe@kernel.dk, p.zabel@pengutronix.de, robh+dt@kernel.org Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, git@xilinx.com, sgoud@xilinx.com, michal.simek@xilinx.com, Piyush Mehta Subject: [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy Date: Tue, 22 Sep 2020 15:45:13 +0530 Message-Id: <1600769713-944-3-git-send-email-piyush.mehta@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600769713-944-1-git-send-email-piyush.mehta@xilinx.com> References: <1600769713-944-1-git-send-email-piyush.mehta@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: b9eea4f7-a92d-4ba2-e281-08d85ee08e9c X-MS-TrafficTypeDiagnostic: MN2PR02MB6638: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fAzhErG1j58+UDl91lTLjfl/HKJUTUBpNmahXgpPVtOPD2rjBKIeCj3bDlg9w3NMdK97zsRxtGZ11E8LN1H/MtzH0tcGCB5F4CUiIvaqnUy+2a9SLL1UW2hkrZJH6FLFGCjwpRSuE0yutkBqop04SDDsVhmwK8lCfe8faBXzJeG25zmAF4e0qQ+1q4BQhILaoEjuaShw6j4S7rgif8R1/4i3D7gsVbvHq+Gitu5r9Gdt5+46svrSG3N2sM2jd7MikA17yrLGJeUYjpSK9PMLYjs8F8vjBl2GdFnc71/ohqmlf2zFCdBEDTz4IFmZ4MJIR8wtlcwUfzqYw7JcQI8l0XissRWztv8POvalcmEAfE1L235MEFqgrkY+CaYe0CQGTrULgRPl1a6Zlz0/xn+aDA== X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFS:(396003)(39860400002)(376002)(136003)(346002)(46966005)(44832011)(26005)(186003)(356005)(36756003)(81166007)(426003)(316002)(336012)(107886003)(82310400003)(4326008)(70206006)(83380400001)(7696005)(70586007)(8936002)(15650500001)(5660300002)(8676002)(47076004)(9786002)(2616005)(2906002)(82740400003)(478600001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2020 10:16:23.1176 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9eea4f7-a92d-4ba2-e281-08d85ee08e9c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT038.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6638 Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy which has 4 GT lanes and can used by 4 peripherals at a time. SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure the GT lane for SATA controller, the below sequence is expected. 1. Assert the SATA controller reset. 2. Configure the xilinx GT phy lane for SATA controller (phy_init). 3. De-assert the SATA controller reset. 4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on). The ahci_platform_enable_resources() by default does the phy_init() and phy_power_on() but the default sequence doesn't work with Xilinx platforms. Because of this reason, updated the driver to support the new sequence. Added is_rst_ctrl flag, for backward compatibility with the older sequence. If the reset controller is not available, then the SATA controller will configure with the older sequences. Signed-off-by: Piyush Mehta --- drivers/ata/ahci_ceva.c | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c index b10fd4c..c704906 100644 --- a/drivers/ata/ahci_ceva.c +++ b/drivers/ata/ahci_ceva.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "ahci.h" /* Vendor Specific Register Offsets */ @@ -87,6 +88,7 @@ struct ceva_ahci_priv { u32 axicc; bool is_cci_enabled; int flags; + struct reset_control *rst; }; static unsigned int ceva_ahci_read_id(struct ata_device *dev, @@ -194,7 +196,7 @@ static int ceva_ahci_probe(struct platform_device *pdev) struct ahci_host_priv *hpriv; struct ceva_ahci_priv *cevapriv; enum dev_dma_attr attr; - int rc; + int rc, i, is_rst_ctrl = 1; cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL); if (!cevapriv) @@ -202,14 +204,47 @@ static int ceva_ahci_probe(struct platform_device *pdev) cevapriv->ahci_pdev = pdev; + cevapriv->rst = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(cevapriv->rst)) { + if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "failed to get reset: %ld\n", + PTR_ERR(cevapriv->rst)); + is_rst_ctrl = 0; + } + hpriv = ahci_platform_get_resources(pdev, 0); if (IS_ERR(hpriv)) return PTR_ERR(hpriv); + if (is_rst_ctrl) + rc = ahci_platform_enable_clks(hpriv); + else + rc = ahci_platform_enable_resources(hpriv); - rc = ahci_platform_enable_resources(hpriv); if (rc) return rc; + if (is_rst_ctrl) { + /* Assert the controller reset */ + reset_control_assert(cevapriv->rst); + + for (i = 0; i < hpriv->nports; i++) { + rc = phy_init(hpriv->phys[i]); + if (rc) + return rc; + } + + /* De-assert the controller reset */ + reset_control_deassert(cevapriv->rst); + + for (i = 0; i < hpriv->nports; i++) { + rc = phy_power_on(hpriv->phys[i]); + if (rc) { + phy_exit(hpriv->phys[i]); + return rc; + } + } + } + if (of_property_read_bool(np, "ceva,broken-gen2")) cevapriv->flags = CEVA_FLAG_BROKEN_GEN2; -- 2.7.4