From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8352BC43613 for ; Mon, 24 Jun 2019 06:16:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 55B3F20663 for ; Mon, 24 Jun 2019 06:16:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727089AbfFXGQu (ORCPT ); Mon, 24 Jun 2019 02:16:50 -0400 Received: from verein.lst.de ([213.95.11.211]:52606 "EHLO newverein.lst.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726343AbfFXGQu (ORCPT ); Mon, 24 Jun 2019 02:16:50 -0400 Received: by newverein.lst.de (Postfix, from userid 2407) id A185E68AFE; Mon, 24 Jun 2019 08:16:17 +0200 (CEST) Date: Mon, 24 Jun 2019 08:16:17 +0200 From: Christoph Hellwig To: Daniel Drake Cc: Christoph Hellwig , Jens Axboe , Keith Busch , Sagi Grimberg , linux-nvme , Linux PCI , Bjorn Helgaas , linux-ide@vger.kernel.org, Linux Upstreaming Team , Linux Kernel , Hannes Reinecke , Alex Williamson , Dan Williams Subject: Re: [PATCH v2 2/5] nvme: rename "pci" operations to "mmio" Message-ID: <20190624061617.GA2848@lst.de> References: <20190620051333.2235-1-drake@endlessm.com> <20190620051333.2235-3-drake@endlessm.com> <20190620061038.GA20564@lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org On Thu, Jun 20, 2019 at 04:11:26PM +0800, Daniel Drake wrote: > On Thu, Jun 20, 2019 at 2:11 PM Christoph Hellwig wrote: > > The Linux NVMe driver will deal with NVMe as specified plus whatever > > minor tweaks we'll need for small bugs. Hiding it behind an AHCI > > device is completely out of scope and will not be accepted. > > Do you have any new suggestions for alternative ways we can implement > support for this storage configuration? IFF we want to support it it has to be done at the PCIe layer. But even that will require actual documentation and support from Intel. If Intel still believes this scheme is their magic secret to control the NVMe market and give themselves and unfair advantage over their competitors there is not much we can do.