From: Gwendal Grignou <gwendal@chromium.org>
To: tj@kernel.org, sergei.shtylyov@gmail.com
Cc: linux-ide@vger.kernel.org, Gwendal Grignou <gwendal@chromium.org>
Subject: [PATCH v2 2/2] driver: ahci: Disable DLPM on Fizz chromebox
Date: Mon, 22 Mar 2021 01:08:38 -0700 [thread overview]
Message-ID: <20210322080838.1640805-3-gwendal@chromium.org> (raw)
In-Reply-To: <20210322080838.1640805-1-gwendal@chromium.org>
On Chromebox Fizz platform, (HP Chromebox G2, ASUS Chromebox 3, ...),
hard CPU freeze were observed when the SSD DLPM is engaged at
'min_power'.
Ensure we can not change the |link_power_management_policy| of the host
controller connected to the root SSD. (Operation not supported).
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
---
No changes in v2.
drivers/ata/ahci.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 9132201f1353e..4b932bb4ed570 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1270,6 +1270,12 @@ static bool ahci_broken_lpm(struct pci_dev *pdev)
*/
.driver_data = "20180310", /* 2.35 */
},
+ {
+ .matches = {
+ DMI_MATCH(DMI_BOARD_VENDOR, "Google"),
+ DMI_MATCH(DMI_BOARD_NAME, "Fizz"),
+ },
+ },
{ } /* terminate list */
};
const struct dmi_system_id *dmi = dmi_first_match(sysids);
--
2.31.0.291.g576ba9dcdaf-goog
prev parent reply other threads:[~2021-03-22 8:09 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-22 8:08 [PATCH v2 0/2] Disable SATA DPLM on Fizz chromebox Gwendal Grignou
2021-03-22 8:08 ` [PATCH v2 1/2] driver: ahci: Allow disabling dlpm for all bios version Gwendal Grignou
2021-03-22 8:08 ` Gwendal Grignou [this message]
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