From: Robin Murphy <robin.murphy@arm.com>
To: David Laight <David.Laight@ACULAB.COM>,
Hans de Goede <hdegoede@redhat.com>,
Roger Quadros <rogerq@ti.com>,
"axboe@kernel.dk" <axboe@kernel.dk>
Cc: "vigneshr@ti.com" <vigneshr@ti.com>,
"nsekhar@ti.com" <nsekhar@ti.com>,
"linux-ide@vger.kernel.org" <linux-ide@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"stable@vger.kernel.org" <stable@vger.kernel.org>,
"Christoph Hellwig" <hch@lst.de>,
"Rob Herring" <robh+dt@kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"Kishon Vijay Abraham I" <kishon@ti.com>,
"Péter Ujfalusi" <peter.ujfalusi@ti.com>
Subject: Re: [PATCH] ata: ahci_platform: add 32-bit quirk for dwc-ahci
Date: Wed, 12 Feb 2020 12:09:49 +0000 [thread overview]
Message-ID: <2f82cd89-a1c2-cf47-97df-3acac0798c85@arm.com> (raw)
In-Reply-To: <2a527d21087b4f959c7f95895d70b669@AcuMS.aculab.com>
On 2020-02-12 11:56 am, David Laight wrote:
> From: Robin Murphy
>> Sent: 12 February 2020 11:43
> ...
>> If the device *is* inherently 64-bit capable, then setting 64-bit masks
>> in the driver is correct - if a 64-bit IP block happens to have been
>> integrated with only 32 address bits wired up, but the system has memory
>> above the 32-bit boundary, then that should be described via
>> "dma-ranges", which should then end up being used to further constrain
>> the device masks internally to the DMA API.
>
> Given how often this happens (please can I shoot some more
> hardware engineers - he says while compiling some VHDL)
> is it possible to allocate some memory pages that are
> aliases if the address bits over 31 are ignored?
>
> Then (at least some) drivers could to a run-time probe
> reading to the high address and checking the data didn't
> appear in the low address.
>
> Only one such set of pages is needed - access can be locked.
> But they'd need to be reserved early on.
(Oh, for that much control over page allocation!)
It's a fun idea, but there's no guarantee that the platform memory map
is actually suitable (AMD Seattle is the go-to counterexample), and
having an opt-in test that every driver has to implement individually
sounds like a maintenance nightmare. I think it's far better all round
to just expect the firmware-provided machine description - be it
devicetree, ACPI, or whatever - to correctly describe the integration.
Robin.
next prev parent reply other threads:[~2020-02-12 12:09 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-06 11:17 [PATCH] ata: ahci_platform: add 32-bit quirk for dwc-ahci Roger Quadros
2020-02-06 11:50 ` Hans de Goede
2020-02-06 11:54 ` Roger Quadros
2020-02-12 11:01 ` Roger Quadros
2020-02-12 11:32 ` Hans de Goede
2020-02-12 11:43 ` Robin Murphy
2020-02-12 11:56 ` David Laight
2020-02-12 12:09 ` Robin Murphy [this message]
2020-02-13 7:24 ` Roger Quadros
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