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[66.29.164.166]) by smtp.gmail.com with ESMTPSA id ce20sm2293923pjb.16.2019.08.12.07.11.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Aug 2019 07:11:24 -0700 (PDT) Subject: Re: [PATCH] ata: ahci: Lookup PCS register offset based on PCI device ID To: Stephen Douthit , Christoph Hellwig Cc: "linux-ide@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Dan Williams References: <20190808202415.25166-1-stephend@silicom-usa.com> <20190810074317.GA18582@infradead.org> From: Jens Axboe Message-ID: <679188f7-bb14-1de6-b533-687809fa7bc8@kernel.dk> Date: Mon, 12 Aug 2019 08:11:22 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org On 8/12/19 6:02 AM, Stephen Douthit wrote: > On 8/10/19 3:43 AM, Christoph Hellwig wrote: >> On Thu, Aug 08, 2019 at 08:24:31PM +0000, Stephen Douthit wrote: >>> Intel moved the PCS register from 0x92 to 0x94 on Denverton for some >>> reason, so now we get to check the device ID before poking it on reset. >> >> And now you just match on the new IDs, which means we'll perpetually >> catch up on any new device. Dan, can you reach out inside Intel to >> figure out if there is a way to find out the PCS register location >> without the PCI ID check? >> >> >>> static int ahci_pci_reset_controller(struct ata_host *host) >>> { >>> struct pci_dev *pdev = to_pci_dev(host->dev); >>> @@ -634,13 +669,14 @@ static int ahci_pci_reset_controller(struct ata_host *host) >>> >>> if (pdev->vendor == PCI_VENDOR_ID_INTEL) { >>> struct ahci_host_priv *hpriv = host->private_data; >>> + int pcs = ahci_pcs_offset(host); >>> u16 tmp16; >>> >>> /* configure PCS */ >>> - pci_read_config_word(pdev, 0x92, &tmp16); >>> + pci_read_config_word(pdev, pcs, &tmp16); >>> if ((tmp16 & hpriv->port_map) != hpriv->port_map) { >>> - tmp16 |= hpriv->port_map; >>> - pci_write_config_word(pdev, 0x92, tmp16); >>> + tmp16 |= hpriv->port_map & 0xff; >>> + pci_write_config_word(pdev, pcs, tmp16); >>> } >>> } >> >> And Stephen, while you are at it, can you split this Intel-specific >> quirk into a separate helper? > > I can do that. I'll wait until we hear back from Dan if there's a > better scheme than a device ID lookup. I'll drop the previous series for now. -- Jens Axboe