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[66.29.164.166]) by smtp.gmail.com with ESMTPSA id e2sm8130595pff.49.2019.08.30.19.54.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Aug 2019 19:54:06 -0700 (PDT) Subject: Re: [PATCH v3] libata/ahci: Drop PCS quirk for Denverton and beyond To: Dan Williams Cc: Stephen Douthit , Christoph Hellwig , linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org References: <156712139395.1614755.3489977733530873708.stgit@dwillia2-desk3.amr.corp.intel.com> From: Jens Axboe Message-ID: <73e48d44-631a-71f9-4437-292c5b480891@kernel.dk> Date: Fri, 30 Aug 2019 20:54:04 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <156712139395.1614755.3489977733530873708.stgit@dwillia2-desk3.amr.corp.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org On 8/29/19 5:30 PM, Dan Williams wrote: > The Linux ahci driver has historically implemented a configuration fixup > for platforms / platform-firmware that fails to enable the ports prior > to OS hand-off at boot. The fixup was originally implemented way back > before ahci moved from drivers/scsi/ to drivers/ata/, and was updated in > 2007 via commit 49f290903935 "ahci: update PCS programming". The quirk > sets a port-enable bitmap in the PCS register at offset 0x92. > > This quirk could be applied generically up until the arrival of the > Denverton (DNV) platform. The DNV AHCI controller architecture supports > more than 6 ports and along with that the PCS register location and > format were updated to allow for more possible ports in the bitmap. DNV > AHCI expands the register to 32-bits and moves it to offset 0x94. > > As it stands there are no known problem reports with existing Linux > trying to set bits at offset 0x92 which indicates that the quirk is not > applicable. Likely it is not applicable on a wider range of platforms, > but it is difficult to discern which platforms if any still depend on > the quirk. > > Rather than try to fix the PCS quirk to consider the DNV register layout > instead require explicit opt-in. The assumption is that the OS driver > need not touch this register, and platforms can be added with a new > boad_ahci_pcs7 board-id when / if problematic platforms are found in the > future. The logic in ahci_intel_pcs_quirk() looks for all Intel AHCI > instances with "legacy" board-ids and otherwise skips the quirk if the > board was matched by class-code. Applied, thanks Dan. -- Jens Axboe