From: Ioannis Barkas <jnyb.de@gmail.com>
To: linux-ide@vger.kernel.org
Subject: Re: [PATCH v3] libata/ahci: Drop PCS quirk for Denverton and beyond
Date: Tue, 3 Sep 2019 14:21:41 +0300 [thread overview]
Message-ID: <CADUzMVYrdSJYnpS+qiP=cLFshvP7PKYF6CPiufJEaRVmBVFdVA@mail.gmail.com> (raw)
Hello guys,
Catching up with the Denverton converstion feels like a deja vu as
this isn't the first time I am looking at datasheets to find out what
engineers have modified this time on intel chipsets.
After carefully reading some datasheets, it is clear that this patch
has a no go. That is because the DNV isn't the only PCH using PCS at
offset 94. The same offset is used at Union Point(200 series) as well
as Lewisburg(C620-series) PCH. As a result, this patch will ensure
offset 92 is used for Lewisburg IDs A182, A186, A202 & A206. In
reality those devices use offset 94 so please be careful here as
things may get nasty. Please assign all devices using offset 94 for
the PCS register to board_ahci_pcs7.
While at it, I have seen that Intel C620 uses device 2822 & 2826.
While 2826 can be added, 2822 has a duplicate entry:
{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
This doesn't look good. On ICH8 we need to disable Asynchronous
Notification but which one is applied to Lewisburg? The SNTF one?
It gets more interesting as C620 RSTe 0x2822 uses offset 94 not 92. A
new patch must handle all those chipsets having a different version of
the SATA controller.
next reply other threads:[~2019-09-03 11:21 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-03 11:21 Ioannis Barkas [this message]
-- strict thread matches above, loose matches on Subject: below --
2019-08-29 23:30 [PATCH v3] libata/ahci: Drop PCS quirk for Denverton and beyond Dan Williams
2019-08-30 15:47 ` Stephen Douthit
2019-08-30 16:00 ` Dan Williams
2019-08-30 17:05 ` Stephen Douthit
2019-08-31 2:54 ` Jens Axboe
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