From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08FA4C433F5 for ; Tue, 21 Sep 2021 05:29:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD48661159 for ; Tue, 21 Sep 2021 05:29:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229561AbhIUFan (ORCPT ); Tue, 21 Sep 2021 01:30:43 -0400 Received: from mx24.baidu.com ([111.206.215.185]:50026 "EHLO baidu.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S229441AbhIUFal (ORCPT ); Tue, 21 Sep 2021 01:30:41 -0400 Received: from BJHW-Mail-Ex05.internal.baidu.com (unknown [10.127.64.15]) by Forcepoint Email with ESMTPS id 378BD4D901B219A99263; Tue, 21 Sep 2021 13:28:41 +0800 (CST) Received: from BJHW-MAIL-EX27.internal.baidu.com (10.127.64.42) by BJHW-Mail-Ex05.internal.baidu.com (10.127.64.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 21 Sep 2021 13:28:41 +0800 Received: from LAPTOP-UKSR4ENP.internal.baidu.com (172.31.63.8) by BJHW-MAIL-EX27.internal.baidu.com (10.127.64.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 21 Sep 2021 13:28:39 +0800 From: Cai Huoqing To: CC: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Shawn Guo , "Sascha Hauer" , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , , , , Subject: [PATCH v5 2/3] iio: imx8qxp-adc: dt-bindings: iio: adc: Add binding documentation for NXP IMX8QXP ADC Date: Tue, 21 Sep 2021 13:28:14 +0800 Message-ID: <20210921052821.91-3-caihuoqing@baidu.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210921052821.91-1-caihuoqing@baidu.com> References: <20210921052821.91-1-caihuoqing@baidu.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.31.63.8] X-ClientProxiedBy: BC-Mail-Ex13.internal.baidu.com (172.31.51.53) To BJHW-MAIL-EX27.internal.baidu.com (10.127.64.42) X-Baidu-BdMsfe-DateCheck: 1_BJHW-Mail-Ex05_2021-09-21 13:28:41:292 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org The NXP i.MX 8QuadXPlus SOC a new ADC IP, so add binding documentation for NXP IMX8QXP ADC. Signed-off-by: Cai Huoqing --- v1->v2: *Fix some indentation issues. *Mark status as okay. *Change clock2 source. v3->v4: *Remove 'status' from examples. *Remove unused 'state'. *Remove interrupts-parent. *Change num of address/size-cells from 1 to 2. v4->v5: *Remove unused properties v1 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210830172140.414-5-caihuoqing@baidu.com/ v3 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210907015724.1377-3-caihuoqing@baidu.com/ v4 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210912071334.1745-3-caihuoqing@baidu.com/ .../bindings/iio/adc/nxp,imx8qxp-adc.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml new file mode 100644 index 000000000000..9c59a20a6032 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP IMX8QXP ADC bindings + +maintainers: + - Cai Huoqing + +description: + Supports the ADC found on the IMX8QXP SoC. + +properties: + compatible: + const: nxp,imx8qxp-adc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: per + - const: ipg + + assigned-clocks: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - assigned-clocks + - assigned-clock-rates + - power-domains + - "#io-channel-cells" + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + adc@5a880000 { + compatible = "nxp,imx8qxp-adc"; + reg = <0x0 0x5a880000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX_SC_R_ADC_0>, + <&clk IMX_SC_R_ADC_0>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_0>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_0>; + #io-channel-cells = <1>; + }; + }; +... -- 2.25.1