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From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Joerg Roedel <joro@8bytes.org>,
	Jordan Crouse <jcrouse@codeaurora.org>,
	Rob Clark <robdclark@gmail.com>
Cc: linux-arm-msm@vger.kernel.org,
	Sharat Masetty <smasetty@codeaurora.org>,
	Akhil P Oommen <akhilpo@codeaurora.org>,
	dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	iommu@lists.linux-foundation.org,
	"Kristian H . Kristensen" <hoegsberg@google.com>,
	freedreno@lists.freedesktop.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCHv4 3/6] drm/msm: rearrange the gpu_rmw() function
Date: Fri, 11 Sep 2020 14:28:03 +0000	[thread overview]
Message-ID: <010101747d90eb03-5a681419-ff19-4b51-8bf5-1b98ee4569a8-000000@us-west-2.amazonses.com> (raw)
In-Reply-To: <cover.1599832685.git.saiprakash.ranjan@codeaurora.org>

From: Sharat Masetty <smasetty@codeaurora.org>

The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 drivers/gpu/drm/msm/msm_drv.c | 8 ++++++++
 drivers/gpu/drm/msm/msm_drv.h | 1 +
 drivers/gpu/drm/msm/msm_gpu.h | 5 +----
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index abf5799d9a22..03caafa7c7b2 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -180,6 +180,14 @@ u32 msm_readl(const void __iomem *addr)
 	return val;
 }
 
+void msm_rmw(void __iomem *addr, u32 mask, u32 or)
+{
+	u32 val = msm_readl(addr);
+
+	val &= ~mask;
+	msm_writel(val | or, addr);
+}
+
 struct msm_vblank_work {
 	struct work_struct work;
 	int crtc_id;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 2ca9c3c03845..aa07900d9ac4 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -419,6 +419,7 @@ void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
 		const char *dbgname);
 void msm_writel(u32 data, void __iomem *addr);
 u32 msm_readl(const void __iomem *addr);
+void msm_rmw(void __iomem *addr, u32 mask, u32 or);
 
 struct msm_gpu_submitqueue;
 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 5ee358b480e6..1d446b2e5746 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -245,10 +245,7 @@ static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
 
 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
 {
-	uint32_t val = gpu_read(gpu, reg);
-
-	val &= ~mask;
-	gpu_write(gpu, reg, val | or);
+	msm_rmw(gpu->mmio + (reg << 2), mask, or);
 }
 
 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

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  parent reply	other threads:[~2020-09-11 14:28 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <cover.1599832685.git.saiprakash.ranjan@codeaurora.org>
2020-09-11 14:27 ` [PATCHv4 1/6] iommu/io-pgtable-arm: Add support to use system cache Sai Prakash Ranjan
2020-09-11 14:27 ` [PATCHv4 2/6] iommu/arm-smmu: Add domain attribute for " Sai Prakash Ranjan
2020-09-11 14:28 ` Sai Prakash Ranjan [this message]
2020-09-11 14:28 ` [PATCHv4 4/6] drm/msm/a6xx: Add support for using system cache(LLC) Sai Prakash Ranjan
2020-09-11 14:28 ` [PATCHv4 5/6] iommu: arm-smmu-impl: Use table to list QCOM implementations Sai Prakash Ranjan
2020-09-11 14:28 ` [PATCHv4 6/6] iommu: arm-smmu-impl: Remove unwanted extra blank lines Sai Prakash Ranjan
     [not found] ` <010101747d912d9f-c8050b8d-1e81-4be0-ac35-b221f657b490-000000@us-west-2.amazonses.com>
2020-09-11 16:03   ` Robin Murphy
2020-09-11 16:07     ` Will Deacon
2020-09-11 16:21       ` Sai Prakash Ranjan
2020-09-11 16:34         ` Robin Murphy
2020-09-11 16:50           ` Sai Prakash Ranjan
     [not found]           ` <a33160854744942f660fae691a4a30ec@codeaurora.org>
2020-09-15  6:58             ` Sai Prakash Ranjan
2020-09-11 16:19     ` Sai Prakash Ranjan
     [not found] ` <3b1beb6cf6a34a44b0ecff9ec5a2105b5ff91bd4.1599832685.git.saiprakash.ranjan@codeaurora.org>
2020-09-21 18:03   ` [PATCHv4 1/6] iommu/io-pgtable-arm: Add support to use system cache Will Deacon
2020-09-21 22:03     ` Robin Murphy
2020-09-21 22:23       ` Will Deacon
2020-09-22  6:23     ` Sai Prakash Ranjan

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