From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19AF0C282DD for ; Fri, 24 May 2019 01:17:19 +0000 (UTC) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EB72E21841 for ; Fri, 24 May 2019 01:17:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EB72E21841 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=iommu-bounces@lists.linux-foundation.org Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id AEF98108D; Fri, 24 May 2019 01:16:44 +0000 (UTC) Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id CF056F82 for ; Fri, 24 May 2019 01:16:40 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by smtp1.linuxfoundation.org (Postfix) with ESMTPS id D9AD3F4 for ; Fri, 24 May 2019 01:16:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 May 2019 18:16:35 -0700 X-ExtLoop1: 1 Received: from unknown (HELO luv-build.sc.intel.com) ([172.25.110.25]) by fmsmga008.fm.intel.com with ESMTP; 23 May 2019 18:16:35 -0700 From: Ricardo Neri To: Thomas Gleixner , Ingo Molnar , Borislav Petkov Subject: [RFC PATCH v4 05/21] x86/hpet: Reserve timer for the HPET hardlockup detector Date: Thu, 23 May 2019 18:16:07 -0700 Message-Id: <1558660583-28561-6-git-send-email-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558660583-28561-1-git-send-email-ricardo.neri-calderon@linux.intel.com> References: <1558660583-28561-1-git-send-email-ricardo.neri-calderon@linux.intel.com> Cc: Kate Stewart , "Ravi V. Shankar" , x86@kernel.org, Ashok Raj , Arnd Bergmann , Peter Zijlstra , Ricardo Neri , Randy Dunlap , Clemens Ladisch , linux-kernel@vger.kernel.org, Stephane Eranian , Ricardo Neri , "Rafael J. Wysocki" , iommu@lists.linux-foundation.org, Tony Luck , "H. Peter Anvin" , Andi Kleen , Philippe Ombredanne X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: iommu-bounces@lists.linux-foundation.org Errors-To: iommu-bounces@lists.linux-foundation.org HPET timer 2 will be used to drive the HPET-based hardlockup detector. Reserve such timer to ensure it cannot be used by user space programs or for clock events. When looking for MSI-capable timers for clock events, skip timer 2 if the HPET hardlockup detector is selected. Cc: "H. Peter Anvin" Cc: Ashok Raj Cc: Andi Kleen Cc: Tony Luck Cc: Clemens Ladisch Cc: Arnd Bergmann Cc: Philippe Ombredanne Cc: Kate Stewart Cc: "Rafael J. Wysocki" Cc: Stephane Eranian Cc: Suravee Suthikulpanit Cc: "Ravi V. Shankar" Cc: x86@kernel.org Signed-off-by: Ricardo Neri --- arch/x86/include/asm/hpet.h | 3 +++ arch/x86/kernel/hpet.c | 19 ++++++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index e7098740f5ee..6f099e2781ce 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -61,6 +61,9 @@ */ #define HPET_MIN_PERIOD 100000UL +/* Timer used for the hardlockup detector */ +#define HPET_WD_TIMER_NR 2 + /* hpet memory map physical address */ extern unsigned long hpet_address; extern unsigned long force_hpet_address; diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 1723d55219e8..ff0250831786 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -173,7 +173,8 @@ do { \ /* * When the hpet driver (/dev/hpet) is enabled, we need to reserve - * timer 0 and timer 1 in case of RTC emulation. + * timer 0 and timer 1 in case of RTC emulation. Timer 2 is reserved in case + * the HPET-based hardlockup detector is used. */ #ifdef CONFIG_HPET @@ -183,7 +184,7 @@ static void hpet_reserve_platform_timers(unsigned int id) { struct hpet __iomem *hpet = hpet_virt_address; struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; - unsigned int nrtimers, i; + unsigned int nrtimers, i, start_timer; struct hpet_data hd; nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; @@ -198,6 +199,13 @@ static void hpet_reserve_platform_timers(unsigned int id) hpet_reserve_timer(&hd, 1); #endif + if (IS_ENABLED(CONFIG_X86_HARDLOCKUP_DETECTOR_HPET)) { + hpet_reserve_timer(&hd, HPET_WD_TIMER_NR); + start_timer = HPET_WD_TIMER_NR + 1; + } else { + start_timer = HPET_WD_TIMER_NR; + } + /* * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 * is wrong for i8259!) not the output IRQ. Many BIOS writers @@ -206,7 +214,7 @@ static void hpet_reserve_platform_timers(unsigned int id) hd.hd_irq[0] = HPET_LEGACY_8254; hd.hd_irq[1] = HPET_LEGACY_RTC; - for (i = 2; i < nrtimers; timer++, i++) { + for (i = start_timer; i < nrtimers; timer++, i++) { hd.hd_irq[i] = (readl(&timer->hpet_config) & Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; } @@ -651,6 +659,11 @@ static void hpet_msi_capability_lookup(unsigned int start_timer) struct hpet_dev *hdev = &hpet_devs[num_timers_used]; unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); + /* Do not use timer reserved for the HPET watchdog. */ + if (IS_ENABLED(CONFIG_X86_HARDLOCKUP_DETECTOR_HPET) && + i == HPET_WD_TIMER_NR) + continue; + /* Only consider HPET timer with MSI support */ if (!(cfg & HPET_TN_FSB_CAP)) continue; -- 2.17.1 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu