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From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	 Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
	Nicolas Boichat <drinkcat@chromium.org>,
	cui.zhang@mediatek.com, srv_heupstream@mediatek.com,
	chao.hao@mediatek.com, linux-kernel@vger.kernel.org,
	Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
	iommu@lists.linux-foundation.org,
	Rob Herring <robh+dt@kernel.org>,
	linux-mediatek@lists.infradead.org, ming-fan.chen@mediatek.com,
	anan.sun@mediatek.com, Matthias Kaehlcke <mka@chromium.org>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v11 18/23] iommu/mediatek: Add mmu1 support
Date: Sat, 24 Aug 2019 11:02:03 +0800
Message-ID: <1566615728-26388-19-git-send-email-yong.wu@mediatek.com> (raw)
In-Reply-To: <1566615728-26388-1-git-send-email-yong.wu@mediatek.com>

Normally the M4U HW connect EMI with smi. the diagram is like below:
              EMI
               |
              M4U
               |
            smi-common
               |
       -----------------
       |    |    |     |    ...
    larb0 larb1  larb2 larb3

Actually there are 2 mmu cells in the M4U HW, like this diagram:

              EMI
           ---------
            |     |
           mmu0  mmu1     <- M4U
            |     |
           ---------
               |
            smi-common
               |
       -----------------
       |    |    |     |    ...
    larb0 larb1  larb2 larb3

This patch add support for mmu1. In order to get better performance,
we could adjust some larbs go to mmu1 while the others still go to
mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220).

mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default
value of that register is 0 which means all the larbs go to mmu0
defaultly.

This is a preparing patch for adjusting SMI_BUS_SEL for mt8183.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
---
 drivers/iommu/mtk_iommu.c | 46 +++++++++++++++++++++++++++++-----------------
 1 file changed, 29 insertions(+), 17 deletions(-)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index ee3a664..470de8b 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -64,26 +64,32 @@
 #define F_INT_CLR_BIT				BIT(12)
 
 #define REG_MMU_INT_MAIN_CONTROL		0x124
-#define F_INT_TRANSLATION_FAULT			BIT(0)
-#define F_INT_MAIN_MULTI_HIT_FAULT		BIT(1)
-#define F_INT_INVALID_PA_FAULT			BIT(2)
-#define F_INT_ENTRY_REPLACEMENT_FAULT		BIT(3)
-#define F_INT_TLB_MISS_FAULT			BIT(4)
-#define F_INT_MISS_TRANSACTION_FIFO_FAULT	BIT(5)
-#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT	BIT(6)
+						/* mmu0 | mmu1 */
+#define F_INT_TRANSLATION_FAULT			(BIT(0) | BIT(7))
+#define F_INT_MAIN_MULTI_HIT_FAULT		(BIT(1) | BIT(8))
+#define F_INT_INVALID_PA_FAULT			(BIT(2) | BIT(9))
+#define F_INT_ENTRY_REPLACEMENT_FAULT		(BIT(3) | BIT(10))
+#define F_INT_TLB_MISS_FAULT			(BIT(4) | BIT(11))
+#define F_INT_MISS_TRANSACTION_FIFO_FAULT	(BIT(5) | BIT(12))
+#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT	(BIT(6) | BIT(13))
 
 #define REG_MMU_CPE_DONE			0x12C
 
 #define REG_MMU_FAULT_ST1			0x134
+#define F_REG_MMU0_FAULT_MASK			GENMASK(6, 0)
+#define F_REG_MMU1_FAULT_MASK			GENMASK(13, 7)
 
-#define REG_MMU_FAULT_VA			0x13c
+#define REG_MMU0_FAULT_VA			0x13c
 #define F_MMU_FAULT_VA_WRITE_BIT		BIT(1)
 #define F_MMU_FAULT_VA_LAYER_BIT		BIT(0)
 
-#define REG_MMU_INVLD_PA			0x140
-#define REG_MMU_INT_ID				0x150
-#define F_MMU0_INT_ID_LARB_ID(a)		(((a) >> 7) & 0x7)
-#define F_MMU0_INT_ID_PORT_ID(a)		(((a) >> 2) & 0x1f)
+#define REG_MMU0_INVLD_PA			0x140
+#define REG_MMU1_FAULT_VA			0x144
+#define REG_MMU1_INVLD_PA			0x148
+#define REG_MMU0_INT_ID				0x150
+#define REG_MMU1_INT_ID				0x154
+#define F_MMU_INT_ID_LARB_ID(a)			(((a) >> 7) & 0x7)
+#define F_MMU_INT_ID_PORT_ID(a)			(((a) >> 2) & 0x1f)
 
 #define MTK_PROTECT_PA_ALIGN			128
 
@@ -226,13 +232,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 
 	/* Read error info from registers */
 	int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
-	fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
+	if (int_state & F_REG_MMU0_FAULT_MASK) {
+		regval = readl_relaxed(data->base + REG_MMU0_INT_ID);
+		fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA);
+		fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA);
+	} else {
+		regval = readl_relaxed(data->base + REG_MMU1_INT_ID);
+		fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA);
+		fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA);
+	}
 	layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
 	write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
-	fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
-	regval = readl_relaxed(data->base + REG_MMU_INT_ID);
-	fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
-	fault_port = F_MMU0_INT_ID_PORT_ID(regval);
+	fault_larb = F_MMU_INT_ID_LARB_ID(regval);
+	fault_port = F_MMU_INT_ID_PORT_ID(regval);
 
 	fault_larb = data->plat_data->larbid_remap[fault_larb];
 
-- 
1.9.1

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  parent reply index

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-24  3:01 [PATCH v11 00/23] MT8183 IOMMU SUPPORT Yong Wu
2019-08-24  3:01 ` [PATCH v11 01/23] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI Yong Wu
2019-08-24  3:01 ` [PATCH v11 02/23] iommu/mediatek: Use a struct as the platform data Yong Wu
2019-08-24  3:01 ` [PATCH v11 03/23] memory: mtk-smi: Use a general config_port interface Yong Wu
2019-08-24  3:01 ` [PATCH v11 04/23] memory: mtk-smi: Use a struct for the platform data for smi-common Yong Wu
2019-08-24  3:01 ` [PATCH v11 05/23] iommu/mediatek: Fix iova_to_phys PA start for 4GB mode Yong Wu
2019-08-24  3:01 ` [PATCH v11 06/23] iommu/io-pgtable-arm-v7s: Add paddr_to_iopte and iopte_to_paddr helpers Yong Wu
2019-08-24  3:01 ` [PATCH v11 07/23] iommu/io-pgtable-arm-v7s: Use ias/oas to check the valid iova/pa Yong Wu
2019-08-24  3:01 ` [PATCH v11 08/23] iommu/io-pgtable-arm-v7s: Rename the quirk from MTK_4GB to MTK_EXT Yong Wu
2019-08-24  3:01 ` [PATCH v11 09/23] iommu/io-pgtable-arm-v7s: Extend to support PA[33:32] for MediaTek Yong Wu
2019-08-24  3:01 ` [PATCH v11 10/23] iommu/mediatek: Adjust the PA for the 4GB Mode Yong Wu
2019-08-24  3:01 ` [PATCH v11 11/23] iommu/mediatek: Add bclk can be supported optionally Yong Wu
2019-08-24  3:01 ` [PATCH v11 12/23] iommu/mediatek: Add larb-id remapped support Yong Wu
2019-08-24  3:01 ` [PATCH v11 13/23] iommu/mediatek: Refine protect memory definition Yong Wu
2019-08-24  3:01 ` [PATCH v11 14/23] iommu/mediatek: Move reset_axi into plat_data Yong Wu
2019-08-24  3:02 ` [PATCH v11 15/23] iommu/mediatek: Move vld_pa_rng " Yong Wu
2019-08-24  3:02 ` [PATCH v11 16/23] memory: mtk-smi: Add gals support Yong Wu
2019-08-24  3:02 ` [PATCH v11 17/23] iommu/mediatek: Add mt8183 IOMMU support Yong Wu
2019-08-24  3:02 ` Yong Wu [this message]
2019-08-24  3:02 ` [PATCH v11 19/23] memory: mtk-smi: Invoke pm runtime_callback to enable clocks Yong Wu
2019-08-24  3:02 ` [PATCH v11 20/23] memory: mtk-smi: Add bus_sel for mt8183 Yong Wu
2019-08-24  3:02 ` [PATCH v11 21/23] iommu/mediatek: Fix VLD_PA_RNG register backup when suspend Yong Wu
2019-08-24  3:02 ` [PATCH v11 22/23] memory: mtk-smi: Get rid of need_larbid Yong Wu
2019-08-24  3:02 ` [PATCH v11 23/23] iommu/mediatek: Clean up struct mtk_smi_iommu Yong Wu
2019-08-24 11:57 ` [PATCH v11 00/23] MT8183 IOMMU SUPPORT Will Deacon
2019-08-30 14:21 ` Joerg Roedel

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