From: Krishna Reddy <vdumpa@nvidia.com>
Cc: snikam@nvidia.com, thomasz@nvidia.com, jtukkinen@nvidia.com,
mperttunen@nvidia.com, will@kernel.org,
linux-kernel@vger.kernel.org, praithatha@nvidia.com,
talho@nvidia.com, iommu@lists.linux-foundation.org,
linux-tegra@vger.kernel.org, yhsu@nvidia.com, treding@nvidia.com,
robin.murphy@arm.com, avanbrunt@nvidia.com,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/7] iommu/arm-smmu: prepare arm_smmu_flush_ops for override
Date: Mon, 2 Sep 2019 20:32:02 -0700 [thread overview]
Message-ID: <1567481528-31163-2-git-send-email-vdumpa@nvidia.com> (raw)
In-Reply-To: <1567481528-31163-1-git-send-email-vdumpa@nvidia.com>
Remove const keyword for arm_smmu_flush_ops in arm_smmu_domain
and replace direct references to arm_smmu_tlb_sync* functions with
arm_smmu_flush_ops->tlb_sync().
This is necessary for vendor specific implementations that
need to override arm_smmu_flush_ops in part or full.
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
---
drivers/iommu/arm-smmu.c | 16 ++++++++--------
drivers/iommu/arm-smmu.h | 4 +++-
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 5b93c79..16b5c54 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -52,9 +52,6 @@
*/
#define QCOM_DUMMY_VAL -1
-#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
-#define TLB_SPIN_COUNT 10
-
#define MSI_IOVA_BASE 0x8000000
#define MSI_IOVA_LENGTH 0x100000
@@ -290,6 +287,8 @@ static void arm_smmu_tlb_sync_vmid(void *cookie)
static void arm_smmu_tlb_inv_context_s1(void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
+ const struct arm_smmu_flush_ops *ops = smmu_domain->flush_ops;
+
/*
* The TLBI write may be relaxed, so ensure that PTEs cleared by the
* current CPU are visible beforehand.
@@ -297,18 +296,19 @@ static void arm_smmu_tlb_inv_context_s1(void *cookie)
wmb();
arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx,
ARM_SMMU_CB_S1_TLBIASID, smmu_domain->cfg.asid);
- arm_smmu_tlb_sync_context(cookie);
+ ops->tlb_sync(cookie);
}
static void arm_smmu_tlb_inv_context_s2(void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
struct arm_smmu_device *smmu = smmu_domain->smmu;
+ const struct arm_smmu_flush_ops *ops = smmu_domain->flush_ops;
/* See above */
wmb();
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid);
- arm_smmu_tlb_sync_global(smmu);
+ ops->tlb_sync(cookie);
}
static void arm_smmu_tlb_inv_range_s1(unsigned long iova, size_t size,
@@ -410,7 +410,7 @@ static void arm_smmu_tlb_add_page(struct iommu_iotlb_gather *gather,
ops->tlb_inv_range(iova, granule, granule, true, cookie);
}
-static const struct arm_smmu_flush_ops arm_smmu_s1_tlb_ops = {
+static struct arm_smmu_flush_ops arm_smmu_s1_tlb_ops = {
.tlb = {
.tlb_flush_all = arm_smmu_tlb_inv_context_s1,
.tlb_flush_walk = arm_smmu_tlb_inv_walk,
@@ -421,7 +421,7 @@ static const struct arm_smmu_flush_ops arm_smmu_s1_tlb_ops = {
.tlb_sync = arm_smmu_tlb_sync_context,
};
-static const struct arm_smmu_flush_ops arm_smmu_s2_tlb_ops_v2 = {
+static struct arm_smmu_flush_ops arm_smmu_s2_tlb_ops_v2 = {
.tlb = {
.tlb_flush_all = arm_smmu_tlb_inv_context_s2,
.tlb_flush_walk = arm_smmu_tlb_inv_walk,
@@ -432,7 +432,7 @@ static const struct arm_smmu_flush_ops arm_smmu_s2_tlb_ops_v2 = {
.tlb_sync = arm_smmu_tlb_sync_context,
};
-static const struct arm_smmu_flush_ops arm_smmu_s2_tlb_ops_v1 = {
+static struct arm_smmu_flush_ops arm_smmu_s2_tlb_ops_v1 = {
.tlb = {
.tlb_flush_all = arm_smmu_tlb_inv_context_s2,
.tlb_flush_walk = arm_smmu_tlb_inv_walk,
diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index b19b6ca..b2d6c7f 100644
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h
@@ -207,6 +207,8 @@ enum arm_smmu_cbar_type {
/* Maximum number of context banks per SMMU */
#define ARM_SMMU_MAX_CBS 128
+#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
+#define TLB_SPIN_COUNT 10
/* Shared driver definitions */
enum arm_smmu_arch_version {
@@ -314,7 +316,7 @@ struct arm_smmu_flush_ops {
struct arm_smmu_domain {
struct arm_smmu_device *smmu;
struct io_pgtable_ops *pgtbl_ops;
- const struct arm_smmu_flush_ops *flush_ops;
+ struct arm_smmu_flush_ops *flush_ops;
struct arm_smmu_cfg cfg;
enum arm_smmu_domain_stage stage;
bool non_strict;
--
2.1.4
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next prev parent reply other threads:[~2019-09-03 3:31 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-03 3:32 [PATCH v2 0/7] Nvidia Arm SMMUv2 Implementation Krishna Reddy
2019-09-03 3:32 ` Krishna Reddy [this message]
2019-09-03 3:32 ` [PATCH v2 2/7] iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage Krishna Reddy
2019-09-03 3:32 ` [PATCH v2 3/7] dt-bindings: arm-smmu: Add binding for Tegra194 SMMU Krishna Reddy
2019-09-03 3:32 ` [PATCH v2 4/7] iommu/arm-smmu: Add global/context fault implementation hooks Krishna Reddy
2019-09-03 3:32 ` [PATCH v2 5/7] arm64: tegra: Add Memory controller DT node on T194 Krishna Reddy
2019-09-03 3:32 ` [PATCH v2 6/7] arm64: tegra: Add DT node for T194 SMMU Krishna Reddy
2019-09-03 3:32 ` [PATCH v2 7/7] arm64: tegra: enable SMMU for SDHCI and EQOS on T194 Krishna Reddy
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