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From: Jacob Pan <jacob.jun.pan@linux.intel.com>
To: iommu@lists.linux-foundation.org,
	LKML <linux-kernel@vger.kernel.org>,
	Joerg Roedel <joro@8bytes.org>,
	"Lu Baolu" <baolu.lu@linux.intel.com>,
	David Woodhouse <dwmw2@infradead.org>
Cc: "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>
Subject: [PATCH v4 2/8] iommu/vt-d: Match CPU and IOMMU paging mode
Date: Thu, 21 Nov 2019 13:26:22 -0800
Message-ID: <1574371588-65634-3-git-send-email-jacob.jun.pan@linux.intel.com> (raw)
In-Reply-To: <1574371588-65634-1-git-send-email-jacob.jun.pan@linux.intel.com>

When setting up first level page tables for sharing with CPU, we need
to ensure IOMMU can support no less than the levels supported by the
CPU.

It is not adequate, as in the current code, to set up 5-level paging
in PASID entry First Level Paging Mode(FLPM) solely based on CPU.

Currently, intel_pasid_setup_first_level() is only used by native SVM
code which already checks paging mode matches. However, future use of
this helper function may not be limited to native SVM.
https://lkml.org/lkml/2019/11/18/1037

Fixes: 437f35e1cd4c8 ("iommu/vt-d: Add first level page table
interface")
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel-pasid.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
index 040a445be300..e7cb0b8a7332 100644
--- a/drivers/iommu/intel-pasid.c
+++ b/drivers/iommu/intel-pasid.c
@@ -499,8 +499,16 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
 	}
 
 #ifdef CONFIG_X86
-	if (cpu_feature_enabled(X86_FEATURE_LA57))
-		pasid_set_flpm(pte, 1);
+	/* Both CPU and IOMMU paging mode need to match */
+	if (cpu_feature_enabled(X86_FEATURE_LA57)) {
+		if (cap_5lp_support(iommu->cap)) {
+			pasid_set_flpm(pte, 1);
+		} else {
+			pr_err("VT-d has no 5-level paging support for CPU\n");
+			pasid_clear_entry(pte);
+			return -EINVAL;
+		}
+	}
 #endif /* CONFIG_X86 */
 
 	pasid_set_domain_id(pte, did);
-- 
2.7.4

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  parent reply index

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-21 21:26 [PATCH v4 0/8] VT-d Native Shared virtual memory cleanup and fixes Jacob Pan
2019-11-21 21:26 ` [PATCH v4 1/8] iommu/vt-d: Fix CPU and IOMMU SVM feature matching checks Jacob Pan
2019-11-21 21:26 ` Jacob Pan [this message]
2019-11-21 21:26 ` [PATCH v4 3/8] iommu/vt-d: Reject SVM bind for failed capability check Jacob Pan
2019-11-21 21:26 ` [PATCH v4 4/8] iommu/vt-d: Avoid duplicated code for PASID setup Jacob Pan
2019-11-21 21:26 ` [PATCH v4 5/8] iommu/vt-d: Fix off-by-one in PASID allocation Jacob Pan
2019-11-21 21:26 ` [PATCH v4 6/8] iommu/vt-d: Replace Intel specific PASID allocator with IOASID Jacob Pan
2019-11-21 21:26 ` [PATCH v4 7/8] iommu/vt-d: Avoid sending invalid page response Jacob Pan
2019-11-21 21:26 ` [PATCH v4 8/8] iommu/vt-d: Misc macro clean up for SVM Jacob Pan
2019-11-21 21:37   ` Joe Perches
2019-12-02 18:15     ` Jacob Pan
2019-12-02 18:22       ` Joe Perches
2019-12-02 19:51         ` Jacob Pan

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