From: Fenghua Yu <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
"Joerg Roedel" <joro@8bytes.org>,
"Ingo Molnar" <mingo@redhat.com>,
"Borislav Petkov" <bp@alien8.de>,
"Peter Zijlstra" <peterz@infradead.org>,
"H Peter Anvin" <hpa@zytor.com>,
"David Woodhouse" <dwmw2@infradead.org>,
"Lu Baolu" <baolu.lu@linux.intel.com>,
"Felix Kuehling" <Felix.Kuehling@amd.com>,
"Dave Hansen" <dave.hansen@intel.com>,
"Tony Luck" <tony.luck@intel.com>,
"Jean-Philippe Brucker" <jean-philippe@linaro.org>,
"Christoph Hellwig" <hch@infradead.org>,
"Ashok Raj" <ashok.raj@intel.com>,
"Jacob Jun Pan" <jacob.jun.pan@intel.com>,
"Dave Jiang" <dave.jiang@intel.com>,
"Sohil Mehta" <sohil.mehta@intel.com>,
"Ravi V Shankar" <ravi.v.shankar@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
iommu@lists.linux-foundation.org, x86 <x86@kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
amd-gfx <amd-gfx@lists.freedesktop.org>
Subject: [PATCH v5 06/12] x86/msr-index: Define IA32_PASID MSR
Date: Tue, 30 Jun 2020 16:44:36 -0700 [thread overview]
Message-ID: <1593560682-40814-7-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1593560682-40814-1-git-send-email-fenghua.yu@intel.com>
The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier
(PASID), a 20-bit value. Bit 31 must be set to indicate the value
programmed in the MSR is valid. Hardware uses PASID to identify process
address space and direct responses to the right address space.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
---
v2:
- Change "identify process" to "identify process address space" in the
commit message (Thomas)
arch/x86/include/asm/msr-index.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index e8370e64a155..e5f699ff1dd6 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -237,6 +237,9 @@
#define MSR_IA32_LASTINTFROMIP 0x000001dd
#define MSR_IA32_LASTINTTOIP 0x000001de
+#define MSR_IA32_PASID 0x00000d93
+#define MSR_IA32_PASID_VALID BIT_ULL(31)
+
/* DEBUGCTLMSR bits (others vary by model): */
#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
#define DEBUGCTLMSR_BTF_SHIFT 1
--
2.19.1
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next prev parent reply other threads:[~2020-06-30 23:45 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-30 23:44 [PATCH v5 00/12] x86: tag application address space for devices Fenghua Yu
2020-06-30 23:44 ` [PATCH v5 01/12] iommu: Change type of pasid to u32 Fenghua Yu
2020-07-01 2:12 ` Felix Kuehling
2020-07-02 19:10 ` Fenghua Yu
2020-07-03 5:32 ` Felix Kuehling
2020-06-30 23:44 ` [PATCH v5 02/12] iommu/vt-d: Change flags type to unsigned int in binding mm Fenghua Yu
2020-06-30 23:44 ` [PATCH v5 03/12] docs: x86: Add documentation for SVA (Shared Virtual Addressing) Fenghua Yu
2020-06-30 23:44 ` [PATCH v5 04/12] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Fenghua Yu
2020-06-30 23:44 ` [PATCH v5 05/12] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature Fenghua Yu
2020-06-30 23:44 ` Fenghua Yu [this message]
2020-06-30 23:44 ` [PATCH v5 07/12] mm: Define pasid in mm Fenghua Yu
2020-06-30 23:44 ` [PATCH v5 08/12] fork: Clear PASID for new mm Fenghua Yu
2020-06-30 23:44 ` [PATCH v5 09/12] x86/process: Clear PASID state for a newly forked/cloned thread Fenghua Yu
2020-06-30 23:44 ` [PATCH v5 10/12] x86/mmu: Allocate/free PASID Fenghua Yu
2020-06-30 23:44 ` [PATCH v5 11/12] sched: Define and initialize a flag to identify valid PASID in the task Fenghua Yu
2020-06-30 23:44 ` [PATCH v5 12/12] x86/traps: Fix up invalid PASID Fenghua Yu
2020-07-07 21:30 ` [PATCH v5 00/12] x86: tag application address space for devices Fenghua Yu
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