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From: Fenghua Yu <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
	"Ingo Molnar" <mingo@redhat.com>,
	"Borislav Petkov" <bp@alien8.de>, "H Peter Anvin" <hpa@zytor.com>,
	"Andy Lutomirski" <luto@kernel.org>,
	"Jean-Philippe Brucker" <jean-philippe@linaro.org>,
	"Christoph Hellwig" <hch@infradead.org>,
	"Peter Zijlstra" <peterz@infradead.org>,
	"David Woodhouse" <dwmw2@infradead.org>,
	"Lu Baolu" <baolu.lu@linux.intel.com>,
	"Dave Hansen" <dave.hansen@intel.com>,
	"Tony Luck" <tony.luck@intel.com>,
	"Ashok Raj" <ashok.raj@intel.com>,
	"Jacob Jun Pan" <jacob.jun.pan@intel.com>,
	"Dave Jiang" <dave.jiang@intel.com>,
	"Sohil Mehta" <sohil.mehta@intel.com>,
	"Ravi V Shankar" <ravi.v.shankar@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
	iommu@lists.linux-foundation.org, x86 <x86@kernel.org>,
	linux-kernel <linux-kernel@vger.kernel.org>
Subject: [PATCH v7 6/9] x86/msr-index: Define IA32_PASID MSR
Date: Thu, 27 Aug 2020 08:06:31 -0700	[thread overview]
Message-ID: <1598540794-132666-7-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1598540794-132666-1-git-send-email-fenghua.yu@intel.com>

The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier
(PASID), a 20-bit value. Bit 31 must be set to indicate the value
programmed in the MSR is valid. Hardware uses PASID to identify process
address space and direct responses to the right address space.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
---
v2:
- Change "identify process" to "identify process address space" in the
  commit message (Thomas)

 arch/x86/include/asm/msr-index.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 2859ee4f39a8..aaddc6a9e237 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -257,6 +257,9 @@
 #define MSR_IA32_LASTINTFROMIP		0x000001dd
 #define MSR_IA32_LASTINTTOIP		0x000001de
 
+#define MSR_IA32_PASID			0x00000d93
+#define MSR_IA32_PASID_VALID		BIT_ULL(31)
+
 /* DEBUGCTLMSR bits (others vary by model): */
 #define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */
 #define DEBUGCTLMSR_BTF_SHIFT		1
-- 
2.19.1

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  parent reply	other threads:[~2020-08-27 15:07 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-27 15:06 [PATCH v7 0/9] x86: tag application address space for devices Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 1/9] iommu: Change type of pasid to u32 Fenghua Yu
2020-09-04 10:46   ` Borislav Petkov
2020-09-04 16:06     ` Fenghua Yu
2020-09-04 19:45       ` Borislav Petkov
2020-09-04 20:47         ` Fenghua Yu
2020-09-04 20:53           ` Borislav Petkov
2020-08-27 15:06 ` [PATCH v7 2/9] iommu/vt-d: Change flags type to unsigned int in binding mm Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 3/9] docs: x86: Add documentation for SVA (Shared Virtual Addressing) Fenghua Yu
2020-09-05 15:14   ` Borislav Petkov
2020-09-05 17:54   ` Randy Dunlap
2020-09-15  2:02     ` Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 4/9] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 5/9] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature Fenghua Yu
2020-08-27 15:06 ` Fenghua Yu [this message]
2020-08-27 15:06 ` [PATCH v7 7/9] mm: Define pasid in mm Fenghua Yu
2020-08-27 15:06 ` [PATCH v7 8/9] x86/cpufeatures: Mark ENQCMD as disabled when configured out Fenghua Yu
2020-09-07 10:29   ` Borislav Petkov
2020-08-27 15:06 ` [PATCH v7 9/9] x86/mmu: Allocate/free PASID Fenghua Yu
2020-09-03 22:34   ` Fenghua Yu
2020-09-07 11:18   ` Borislav Petkov
2020-09-14 18:37     ` Fenghua Yu
2020-09-14 19:25       ` Borislav Petkov

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