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From: Jonathan Cameron <Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
To: Jean-Philippe Brucker
	<jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
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	christian.koenig-5C7GfCeVMHo@public.gmane.org
Subject: Re: [PATCH v2 03/40] iommu/sva: Manage process address spaces
Date: Thu, 17 May 2018 15:25:07 +0100
Message-ID: <20180517150516.000067ca@huawei.com> (raw)
In-Reply-To: <20180511190641.23008-4-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>

On Fri, 11 May 2018 20:06:04 +0100
Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> wrote:

> Allocate IOMMU mm structures and binding them to devices. Four operations
> are added to IOMMU drivers:
> 
> * mm_alloc(): to create an io_mm structure and perform architecture-
>   specific operations required to grab the process (for instance on ARM,
>   pin down the CPU ASID so that the process doesn't get assigned a new
>   ASID on rollover).
> 
>   There is a single valid io_mm structure per Linux mm. Future extensions
>   may also use io_mm for kernel-managed address spaces, populated with
>   map()/unmap() calls instead of bound to process address spaces. This
>   patch focuses on "shared" io_mm.
> 
> * mm_attach(): attach an mm to a device. The IOMMU driver checks that the
>   device is capable of sharing an address space, and writes the PASID
>   table entry to install the pgd.
> 
>   Some IOMMU drivers will have a single PASID table per domain, for
>   convenience. Other can implement it differently but to help these
>   drivers, mm_attach and mm_detach take 'attach_domain' and
>   'detach_domain' parameters, that tell whether they need to set and clear
>   the PASID entry or only send the required TLB invalidations.
> 
> * mm_detach(): detach an mm from a device. The IOMMU driver removes the
>   PASID table entry and invalidates the IOTLBs.
> 
> * mm_free(): free a structure allocated by mm_alloc(), and let arch
>   release the process.
> 
> mm_attach and mm_detach operations are serialized with a spinlock. When
> trying to optimize this code, we should at least prevent concurrent
> attach()/detach() on the same domain (so multi-level PASID table code can
> allocate tables lazily). mm_alloc() can sleep, but mm_free must not
> (because we'll have to call it from call_srcu later on).
> 
> At the moment we use an IDR for allocating PASIDs and retrieving contexts.
> We also use a single spinlock. These can be refined and optimized later (a
> custom allocator will be needed for top-down PASID allocation).
> 
> Keeping track of address spaces requires the use of MMU notifiers.
> Handling process exit with regard to unbind() is tricky, so it is left for
> another patch and we explicitly fail mm_alloc() for the moment.
> 
> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>

A few minor bits and bobs inline.  Looks good in general + nice diags!

Thanks,

Jonathan

> 
> ---
> v1->v2: sanity-check of flags
> ---
>  drivers/iommu/iommu-sva.c | 380 +++++++++++++++++++++++++++++++++++++-
>  drivers/iommu/iommu.c     |   1 +
>  include/linux/iommu.h     |  28 +++
>  3 files changed, 406 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/iommu/iommu-sva.c b/drivers/iommu/iommu-sva.c
> index 8d98f9c09864..6ac679c48f3c 100644
> --- a/drivers/iommu/iommu-sva.c
> +++ b/drivers/iommu/iommu-sva.c
> @@ -5,8 +5,298 @@
>   * Copyright (C) 2018 ARM Ltd.
>   */
>  
> +#include <linux/idr.h>
>  #include <linux/iommu.h>
> +#include <linux/sched/mm.h>
>  #include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +/**
> + * DOC: io_mm model
> + *
> + * The io_mm keeps track of process address spaces shared between CPU and IOMMU.
> + * The following example illustrates the relation between structures
> + * iommu_domain, io_mm and iommu_bond. An iommu_bond is a link between io_mm and
> + * device. A device can have multiple io_mm and an io_mm may be bound to
> + * multiple devices.
> + *              ___________________________
> + *             |  IOMMU domain A           |
> + *             |  ________________         |
> + *             | |  IOMMU group   |        +------- io_pgtables
> + *             | |                |        |
> + *             | |   dev 00:00.0 ----+------- bond --- io_mm X
> + *             | |________________|   \    |
> + *             |                       '----- bond ---.
> + *             |___________________________|           \
> + *              ___________________________             \
> + *             |  IOMMU domain B           |           io_mm Y
> + *             |  ________________         |           / /
> + *             | |  IOMMU group   |        |          / /
> + *             | |                |        |         / /
> + *             | |   dev 00:01.0 ------------ bond -' /
> + *             | |   dev 00:01.1 ------------ bond --'
> + *             | |________________|        |
> + *             |                           +------- io_pgtables
> + *             |___________________________|
> + *
> + * In this example, device 00:00.0 is in domain A, devices 00:01.* are in domain
> + * B. All devices within the same domain access the same address spaces. Device
> + * 00:00.0 accesses address spaces X and Y, each corresponding to an mm_struct.
> + * Devices 00:01.* only access address space Y. In addition each
> + * IOMMU_DOMAIN_DMA domain has a private address space, io_pgtable, that is
> + * managed with iommu_map()/iommu_unmap(), and isn't shared with the CPU MMU.
> + *
> + * To obtain the above configuration, users would for instance issue the
> + * following calls:
> + *
> + *     iommu_sva_bind_device(dev 00:00.0, mm X, ...) -> PASID 1
> + *     iommu_sva_bind_device(dev 00:00.0, mm Y, ...) -> PASID 2
> + *     iommu_sva_bind_device(dev 00:01.0, mm Y, ...) -> PASID 2
> + *     iommu_sva_bind_device(dev 00:01.1, mm Y, ...) -> PASID 2
> + *
> + * A single Process Address Space ID (PASID) is allocated for each mm. In the
> + * example, devices use PASID 1 to read/write into address space X and PASID 2
> + * to read/write into address space Y.
> + *
> + * Hardware tables describing this configuration in the IOMMU would typically
> + * look like this:
> + *
> + *                                PASID tables
> + *                                 of domain A
> + *                              .->+--------+
> + *                             / 0 |        |-------> io_pgtable
> + *                            /    +--------+
> + *            Device tables  /   1 |        |-------> pgd X
> + *              +--------+  /      +--------+
> + *      00:00.0 |      A |-'     2 |        |--.
> + *              +--------+         +--------+   \
> + *              :        :       3 |        |    \
> + *              +--------+         +--------+     --> pgd Y
> + *      00:01.0 |      B |--.                    /
> + *              +--------+   \                  |
> + *      00:01.1 |      B |----+   PASID tables  |
> + *              +--------+     \   of domain B  |
> + *                              '->+--------+   |
> + *                               0 |        |-- | --> io_pgtable
> + *                                 +--------+   |
> + *                               1 |        |   |
> + *                                 +--------+   |
> + *                               2 |        |---'
> + *                                 +--------+
> + *                               3 |        |
> + *                                 +--------+
> + *
> + * With this model, a single call binds all devices in a given domain to an
> + * address space. Other devices in the domain will get the same bond implicitly.
> + * However, users must issue one bind() for each device, because IOMMUs may
> + * implement SVA differently. Furthermore, mandating one bind() per device
> + * allows the driver to perform sanity-checks on device capabilities.
> + *
> + * On Arm and AMD IOMMUs, entry 0 of the PASID table can be used to hold
> + * non-PASID translations. In this case PASID 0 is reserved and entry 0 points
> + * to the io_pgtable base. On Intel IOMMU, the io_pgtable base would be held in
> + * the device table and PASID 0 would be available to the allocator.
> + */
> +
> +struct iommu_bond {
> +	struct io_mm		*io_mm;
> +	struct device		*dev;
> +	struct iommu_domain	*domain;
> +
> +	struct list_head	mm_head;
> +	struct list_head	dev_head;
> +	struct list_head	domain_head;
> +
> +	void			*drvdata;
> +};
> +
> +/*
> + * Because we're using an IDR, PASIDs are limited to 31 bits (the sign bit is
> + * used for returning errors). In practice implementations will use at most 20
> + * bits, which is the PCI limit.
> + */
> +static DEFINE_IDR(iommu_pasid_idr);
> +
> +/*
> + * For the moment this is an all-purpose lock. It serializes
> + * access/modifications to bonds, access/modifications to the PASID IDR, and
> + * changes to io_mm refcount as well.
> + */
> +static DEFINE_SPINLOCK(iommu_sva_lock);
> +
> +static struct io_mm *
> +io_mm_alloc(struct iommu_domain *domain, struct device *dev,
> +	    struct mm_struct *mm, unsigned long flags)
> +{
> +	int ret;
> +	int pasid;
> +	struct io_mm *io_mm;
> +	struct iommu_sva_param *param = dev->iommu_param->sva_param;
> +
> +	if (!domain->ops->mm_alloc || !domain->ops->mm_free)
> +		return ERR_PTR(-ENODEV);
> +
> +	io_mm = domain->ops->mm_alloc(domain, mm, flags);
> +	if (IS_ERR(io_mm))
> +		return io_mm;
> +	if (!io_mm)
> +		return ERR_PTR(-ENOMEM);
> +
> +	/*
> +	 * The mm must not be freed until after the driver frees the io_mm
> +	 * (which may involve unpinning the CPU ASID for instance, requiring a
> +	 * valid mm struct.)
> +	 */
> +	mmgrab(mm);
> +
> +	io_mm->flags		= flags;
> +	io_mm->mm		= mm;
> +	io_mm->release		= domain->ops->mm_free;
> +	INIT_LIST_HEAD(&io_mm->devices);
> +
> +	idr_preload(GFP_KERNEL);
> +	spin_lock(&iommu_sva_lock);
> +	pasid = idr_alloc(&iommu_pasid_idr, io_mm, param->min_pasid,
> +			  param->max_pasid + 1, GFP_ATOMIC);

I'd expect the IDR cleanup to be in io_mm_free as that would 'match'
against io_mm_alloc but it's in io_mm_release just before the io_mm_free
call, perhaps move it or am I missing something?

Hmm. This is reworked in patch 5 to use call rcu to do the free.  I suppose
we may be burning an idr entry if we take a while to get round to the
free..  If so a comment to explain this would be great.

> +	io_mm->pasid = pasid;
> +	spin_unlock(&iommu_sva_lock);
> +	idr_preload_end();
> +
> +	if (pasid < 0) {
> +		ret = pasid;
> +		goto err_free_mm;
> +	}
> +
> +	/* TODO: keep track of mm. For the moment, abort. */

>From later patches, I can now see why we didn't init the kref
here, but perhaps a comment would make that clear rather than
people checking it is correctly used throughout?  Actually just grab
the comment from patch 5 and put it in this one and that will
do the job nicely.

> +	ret = -ENOSYS;
> +	spin_lock(&iommu_sva_lock);
> +	idr_remove(&iommu_pasid_idr, io_mm->pasid);
> +	spin_unlock(&iommu_sva_lock);
> +
> +err_free_mm:
> +	domain->ops->mm_free(io_mm);

Really minor, but you now have io_mm->release set so to keep
this obviously the same as the io_mm_free path, perhaps call
that rather than mm_free directly.

> +	mmdrop(mm);
> +
> +	return ERR_PTR(ret);
> +}
> +
> +static void io_mm_free(struct io_mm *io_mm)
> +{
> +	struct mm_struct *mm = io_mm->mm;
> +
> +	io_mm->release(io_mm);
> +	mmdrop(mm);
> +}
> +
> +static void io_mm_release(struct kref *kref)
> +{
> +	struct io_mm *io_mm;
> +
> +	io_mm = container_of(kref, struct io_mm, kref);
> +	WARN_ON(!list_empty(&io_mm->devices));
> +
> +	idr_remove(&iommu_pasid_idr, io_mm->pasid);
> +
> +	io_mm_free(io_mm);
> +}
> +
> +/*
> + * Returns non-zero if a reference to the io_mm was successfully taken.
> + * Returns zero if the io_mm is being freed and should not be used.
> + */
> +static int io_mm_get_locked(struct io_mm *io_mm)
> +{
> +	if (io_mm)
> +		return kref_get_unless_zero(&io_mm->kref);
> +
> +	return 0;
> +}
> +
> +static void io_mm_put_locked(struct io_mm *io_mm)
> +{
> +	kref_put(&io_mm->kref, io_mm_release);
> +}
> +
> +static void io_mm_put(struct io_mm *io_mm)
> +{
> +	spin_lock(&iommu_sva_lock);
> +	io_mm_put_locked(io_mm);
> +	spin_unlock(&iommu_sva_lock);
> +}
> +
> +static int io_mm_attach(struct iommu_domain *domain, struct device *dev,
> +			struct io_mm *io_mm, void *drvdata)
> +{
> +	int ret;
> +	bool attach_domain = true;
> +	int pasid = io_mm->pasid;
> +	struct iommu_bond *bond, *tmp;
> +	struct iommu_sva_param *param = dev->iommu_param->sva_param;
> +
> +	if (!domain->ops->mm_attach || !domain->ops->mm_detach)
> +		return -ENODEV;
> +
> +	if (pasid > param->max_pasid || pasid < param->min_pasid)
> +		return -ERANGE;
> +
> +	bond = kzalloc(sizeof(*bond), GFP_KERNEL);
> +	if (!bond)
> +		return -ENOMEM;
> +
> +	bond->domain		= domain;
> +	bond->io_mm		= io_mm;
> +	bond->dev		= dev;
> +	bond->drvdata		= drvdata;
> +
> +	spin_lock(&iommu_sva_lock);
> +	/*
> +	 * Check if this io_mm is already bound to the domain. In which case the
> +	 * IOMMU driver doesn't have to install the PASID table entry.
> +	 */
> +	list_for_each_entry(tmp, &domain->mm_list, domain_head) {
> +		if (tmp->io_mm == io_mm) {
> +			attach_domain = false;
> +			break;
> +		}
> +	}
> +
> +	ret = domain->ops->mm_attach(domain, dev, io_mm, attach_domain);
> +	if (ret) {
> +		kfree(bond);
> +		spin_unlock(&iommu_sva_lock);
> +		return ret;
> +	}
> +
> +	list_add(&bond->mm_head, &io_mm->devices);
> +	list_add(&bond->domain_head, &domain->mm_list);
> +	list_add(&bond->dev_head, &param->mm_list);
> +	spin_unlock(&iommu_sva_lock);
> +
> +	return 0;
> +}
> +
> +static void io_mm_detach_locked(struct iommu_bond *bond)
> +{
> +	struct iommu_bond *tmp;
> +	bool detach_domain = true;
> +	struct iommu_domain *domain = bond->domain;
> +
> +	list_for_each_entry(tmp, &domain->mm_list, domain_head) {
> +		if (tmp->io_mm == bond->io_mm && tmp->dev != bond->dev) {
> +			detach_domain = false;
> +			break;
> +		}
> +	}
> +
> +	domain->ops->mm_detach(domain, bond->dev, bond->io_mm, detach_domain);
> +

I can't see an immediate reason to have a different order in her to the reverse of
the attach above.   So I think you should be detaching after the list_del calls.
If there is a reason, can we have a comment so I don't ask on v10.

> +	list_del(&bond->mm_head);
> +	list_del(&bond->domain_head);
> +	list_del(&bond->dev_head);
> +	io_mm_put_locked(bond->io_mm);
> +
> +	kfree(bond);
> +}
>  
>  /**
>   * iommu_sva_device_init() - Initialize Shared Virtual Addressing for a device
> @@ -47,6 +337,7 @@ int iommu_sva_device_init(struct device *dev, unsigned long features,
>  
>  	param->features		= features;
>  	param->max_pasid	= max_pasid;
> +	INIT_LIST_HEAD(&param->mm_list);
>  
>  	/*
>  	 * IOMMU driver updates the limits depending on the IOMMU and device
> @@ -114,13 +405,87 @@ EXPORT_SYMBOL_GPL(iommu_sva_device_shutdown);
>  int __iommu_sva_bind_device(struct device *dev, struct mm_struct *mm,
>  			    int *pasid, unsigned long flags, void *drvdata)
>  {
> -	return -ENOSYS; /* TODO */
> +	int i, ret = 0;
> +	struct io_mm *io_mm = NULL;
> +	struct iommu_domain *domain;
> +	struct iommu_bond *bond = NULL, *tmp;
> +	struct iommu_sva_param *param = dev->iommu_param->sva_param;
> +
> +	domain = iommu_get_domain_for_dev(dev);
> +	if (!domain)
> +		return -EINVAL;
> +
> +	/*
> +	 * The device driver does not call sva_device_init/shutdown and
> +	 * bind/unbind concurrently, so no need to take the param lock.
> +	 */
> +	if (WARN_ON_ONCE(!param) || (flags & ~param->features))
> +		return -EINVAL;
> +
> +	/* If an io_mm already exists, use it */
> +	spin_lock(&iommu_sva_lock);
> +	idr_for_each_entry(&iommu_pasid_idr, io_mm, i) {
> +		if (io_mm->mm == mm && io_mm_get_locked(io_mm)) {
> +			/* ... Unless it's already bound to this device */
> +			list_for_each_entry(tmp, &io_mm->devices, mm_head) {
> +				if (tmp->dev == dev) {
> +					bond = tmp;

Using bond for this is clear in a sense, but can we not just use ret
so it is obvious here that we are going to return -EEXIST?
At first glance I thought you were going to carry on with this bond
and couldn't work out why it would ever make sense to have two bonds
between a device an an io_mm (which it doesn't!)

> +					io_mm_put_locked(io_mm);
> +					break;
> +				}
> +			}
> +			break;
> +		}
> +	}
> +	spin_unlock(&iommu_sva_lock);
> +
> +	if (bond)
> +		return -EEXIST;
> +
> +	/* Require identical features within an io_mm for now */
> +	if (io_mm && (flags != io_mm->flags)) {
> +		io_mm_put(io_mm);
> +		return -EDOM;
> +	}
> +
> +	if (!io_mm) {
> +		io_mm = io_mm_alloc(domain, dev, mm, flags);
> +		if (IS_ERR(io_mm))
> +			return PTR_ERR(io_mm);
> +	}
> +
> +	ret = io_mm_attach(domain, dev, io_mm, drvdata);
> +	if (ret)
> +		io_mm_put(io_mm);
> +	else
> +		*pasid = io_mm->pasid;
> +
> +	return ret;
>  }
>  EXPORT_SYMBOL_GPL(__iommu_sva_bind_device);
>  
>  int __iommu_sva_unbind_device(struct device *dev, int pasid)
>  {
> -	return -ENOSYS; /* TODO */
> +	int ret = -ESRCH;
> +	struct iommu_domain *domain;
> +	struct iommu_bond *bond = NULL;
> +	struct iommu_sva_param *param = dev->iommu_param->sva_param;
> +
> +	domain = iommu_get_domain_for_dev(dev);
> +	if (!param || WARN_ON(!domain))
> +		return -EINVAL;
> +
> +	spin_lock(&iommu_sva_lock);
> +	list_for_each_entry(bond, &param->mm_list, dev_head) {
> +		if (bond->io_mm->pasid == pasid) {
> +			io_mm_detach_locked(bond);
> +			ret = 0;
> +			break;
> +		}
> +	}
> +	spin_unlock(&iommu_sva_lock);
> +
> +	return ret;
>  }
>  EXPORT_SYMBOL_GPL(__iommu_sva_unbind_device);
>  
> @@ -132,6 +497,15 @@ EXPORT_SYMBOL_GPL(__iommu_sva_unbind_device);
>   */
>  void __iommu_sva_unbind_dev_all(struct device *dev)
>  {
> -	/* TODO */
> +	struct iommu_sva_param *param;
> +	struct iommu_bond *bond, *next;
> +
> +	param = dev->iommu_param->sva_param;
> +	if (param) {
> +		spin_lock(&iommu_sva_lock);
> +		list_for_each_entry_safe(bond, next, &param->mm_list, dev_head)
> +			io_mm_detach_locked(bond);
> +		spin_unlock(&iommu_sva_lock);
> +	}
>  }
>  EXPORT_SYMBOL_GPL(__iommu_sva_unbind_dev_all);
> diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
> index bd2819deae5b..333801e1519c 100644
> --- a/drivers/iommu/iommu.c
> +++ b/drivers/iommu/iommu.c
> @@ -1463,6 +1463,7 @@ static struct iommu_domain *__iommu_domain_alloc(struct bus_type *bus,
>  	domain->type = type;
>  	/* Assume all sizes by default; the driver may override this later */
>  	domain->pgsize_bitmap  = bus->iommu_ops->pgsize_bitmap;
> +	INIT_LIST_HEAD(&domain->mm_list);
>  
>  	return domain;
>  }
> diff --git a/include/linux/iommu.h b/include/linux/iommu.h
> index da59c20c4f12..d5f21719a5a0 100644
> --- a/include/linux/iommu.h
> +++ b/include/linux/iommu.h
> @@ -100,6 +100,20 @@ struct iommu_domain {
>  	void *handler_token;
>  	struct iommu_domain_geometry geometry;
>  	void *iova_cookie;
> +
> +	struct list_head mm_list;
> +};
> +
> +struct io_mm {
> +	int			pasid;
> +	/* IOMMU_SVA_FEAT_* */
> +	unsigned long		flags;
> +	struct list_head	devices;
> +	struct kref		kref;
> +	struct mm_struct	*mm;
> +
> +	/* Release callback for this mm */
> +	void (*release)(struct io_mm *io_mm);
>  };
>  
>  enum iommu_cap {
> @@ -216,6 +230,7 @@ struct iommu_sva_param {
>  	unsigned long features;
>  	unsigned int min_pasid;
>  	unsigned int max_pasid;
> +	struct list_head mm_list;
>  };
>  
>  /**
> @@ -227,6 +242,11 @@ struct iommu_sva_param {
>   * @detach_dev: detach device from an iommu domain
>   * @sva_device_init: initialize Shared Virtual Adressing for a device
>   * @sva_device_shutdown: shutdown Shared Virtual Adressing for a device
> + * @mm_alloc: allocate io_mm
> + * @mm_free: free io_mm
> + * @mm_attach: attach io_mm to a device. Install PASID entry if necessary
> + * @mm_detach: detach io_mm from a device. Remove PASID entry and
> + *             flush associated TLB entries.
>   * @map: map a physically contiguous memory region to an iommu domain
>   * @unmap: unmap a physically contiguous memory region from an iommu domain
>   * @map_sg: map a scatter-gather list of physically contiguous memory chunks
> @@ -268,6 +288,14 @@ struct iommu_ops {
>  			       struct iommu_sva_param *param);
>  	void (*sva_device_shutdown)(struct device *dev,
>  				    struct iommu_sva_param *param);
> +	struct io_mm *(*mm_alloc)(struct iommu_domain *domain,
> +				  struct mm_struct *mm,
> +				  unsigned long flags);
> +	void (*mm_free)(struct io_mm *io_mm);
> +	int (*mm_attach)(struct iommu_domain *domain, struct device *dev,
> +			 struct io_mm *io_mm, bool attach_domain);
> +	void (*mm_detach)(struct iommu_domain *domain, struct device *dev,
> +			  struct io_mm *io_mm, bool detach_domain);
>  	int (*map)(struct iommu_domain *domain, unsigned long iova,
>  		   phys_addr_t paddr, size_t size, int prot);
>  	size_t (*unmap)(struct iommu_domain *domain, unsigned long iova,

  parent reply index

Thread overview: 123+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-11 19:06 [PATCH v2 00/40] Shared Virtual Addressing for the IOMMU Jean-Philippe Brucker
     [not found] ` <20180511190641.23008-1-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-11 19:06   ` [PATCH v2 01/40] iommu: Introduce Shared Virtual Addressing API Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-2-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-16 20:41       ` Jacob Pan
2018-05-17 10:02         ` Jean-Philippe Brucker
2018-05-17 17:00           ` Jacob Pan
2018-09-05 11:29       ` Auger Eric
     [not found]         ` <bf42affd-e9d0-e4fc-6d28-f3c3f7795348-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2018-09-06 11:09           ` Jean-Philippe Brucker
     [not found]             ` <03d31ba5-1eda-ea86-8c0c-91d14c86fe83-5wv7dgnIgG8@public.gmane.org>
2018-09-06 11:12               ` Christian König
     [not found]                 ` <ed39159c-087e-7e56-7d29-d1de9fa1677f-5C7GfCeVMHo@public.gmane.org>
2018-09-06 12:45                   ` Jean-Philippe Brucker
     [not found]                     ` <f0b317d5-e2e9-5478-952c-05e8b97bd68b-5wv7dgnIgG8@public.gmane.org>
2018-09-07  8:55                       ` Christian König
     [not found]                         ` <2fd4a0a1-1a35-bf82-df84-b995cce011d9-5C7GfCeVMHo@public.gmane.org>
2018-09-07 15:45                           ` Jean-Philippe Brucker
     [not found]                             ` <65e7accd-4446-19f5-c667-c6407e89cfa6-5wv7dgnIgG8@public.gmane.org>
2018-09-07 18:02                               ` Christian König
     [not found]                                 ` <5bbc0332-b94b-75cc-ca42-a9b196811daf-5C7GfCeVMHo@public.gmane.org>
2018-09-07 21:25                                   ` Jacob Pan
2018-09-08  7:29                                     ` Christian König
     [not found]                                       ` <3e3a6797-a233-911b-3a7d-d9b549160960-5C7GfCeVMHo@public.gmane.org>
2018-09-12 12:40                                         ` Jean-Philippe Brucker
     [not found]                                           ` <9445a0be-fb5b-d195-4fdf-7ad6cb36ef4f-5wv7dgnIgG8@public.gmane.org>
2018-09-12 12:56                                             ` Christian König
2018-09-13  7:15                                     ` Tian, Kevin
2018-09-13  7:26                           ` Tian, Kevin
2018-05-11 19:06   ` [PATCH v2 02/40] iommu/sva: Bind process address spaces to devices Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-3-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-17 13:10       ` Jonathan Cameron
     [not found]         ` <20180517141058.00001c76-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:43           ` Jean-Philippe Brucker
2018-09-05 11:29       ` Auger Eric
     [not found]         ` <471873d4-a1a6-1a3a-cf17-1e686b4ade96-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2018-09-06 11:09           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 03/40] iommu/sva: Manage process address spaces Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-4-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-16 23:31       ` Jacob Pan
2018-05-17 10:02         ` Jean-Philippe Brucker
     [not found]           ` <de478769-9f7a-d40b-a55e-e2c63ad883e8-5wv7dgnIgG8@public.gmane.org>
2018-05-22 16:43             ` Jacob Pan
2018-05-24 11:44               ` Jean-Philippe Brucker
2018-05-24 11:50                 ` Ilias Apalodimas
2018-05-24 15:04                   ` Jean-Philippe Brucker
     [not found]                     ` <19e82a74-429a-3f86-119e-32b12082d0ff-5wv7dgnIgG8@public.gmane.org>
2018-05-25  6:33                       ` Ilias Apalodimas
2018-05-25  8:39                         ` Jonathan Cameron
     [not found]                           ` <20180525093959.000040a7-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-26  2:24                             ` Kenneth Lee
2018-05-26  2:24                           ` Kenneth Lee
     [not found]                           ` <20180526022445.GA6069@kllp05>
2018-06-11 16:10                             ` Kenneth Lee
2018-06-11 16:10                             ` Kenneth Lee
2018-06-11 16:32                           ` Kenneth Lee
2018-05-17 14:25       ` Jonathan Cameron [this message]
     [not found]         ` <20180517150516.000067ca-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:44           ` Jean-Philippe Brucker
2018-09-05 12:14       ` Auger Eric
     [not found]         ` <d785ec89-6743-d0f1-1a7f-85599a033e5b-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2018-09-05 18:18           ` Jacob Pan
2018-09-06 17:40             ` Jean-Philippe Brucker
2018-09-06 11:10           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 04/40] iommu/sva: Add a mm_exit callback for device drivers Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-5-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-09-05 13:23       ` Auger Eric
     [not found]         ` <d1dc28c4-7742-9c41-3f91-3fbcb8b13c1c-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2018-09-06 11:10           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 05/40] iommu/sva: Track mm changes with an MMU notifier Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-6-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-17 14:25       ` Jonathan Cameron
     [not found]         ` <20180517152514.00004247-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:44           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 06/40] iommu/sva: Search mm by PASID Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 07/40] iommu: Add a page fault handler Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-8-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-17 15:25       ` Jonathan Cameron
     [not found]         ` <20180517162555.00002bd3-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:48           ` Jean-Philippe Brucker
2018-05-18 18:04       ` Jacob Pan
2018-05-21 14:49         ` Jean-Philippe Brucker
     [not found]           ` <8a640794-a6f3-fa01-82a9-06479a6f779a-5wv7dgnIgG8@public.gmane.org>
2018-05-22 23:35             ` Jacob Pan
2018-05-24 11:44               ` Jean-Philippe Brucker
     [not found]                 ` <bdf9f221-ab97-2168-d072-b7f6a0dba840-5wv7dgnIgG8@public.gmane.org>
2018-05-26  0:35                   ` Jacob Pan
2018-05-29 10:00                     ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 08/40] iommu/iopf: Handle mm faults Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 09/40] iommu/sva: Register page fault handler Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 10/40] mm: export symbol mm_access Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 11/40] mm: export symbol find_get_task_by_vpid Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 12/40] mm: export symbol mmput_async Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 13/40] vfio: Add support for Shared Virtual Addressing Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-14-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-17 15:58       ` Jonathan Cameron
     [not found]         ` <20180517165845.00000cc9-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:51           ` Jean-Philippe Brucker
2018-05-23  9:38       ` Xu Zaibo
     [not found]         ` <5B0536A3.1000304-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-24 11:44           ` Jean-Philippe Brucker
     [not found]             ` <cd13f60d-b282-3804-4ca7-2d34476c597f-5wv7dgnIgG8@public.gmane.org>
2018-05-24 12:35               ` Xu Zaibo
     [not found]                 ` <5B06B17C.1090809-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-24 15:04                   ` Jean-Philippe Brucker
     [not found]                     ` <205c1729-8026-3efe-c363-d37d7150d622-5wv7dgnIgG8@public.gmane.org>
2018-05-25  2:39                       ` Xu Zaibo
2018-05-25  9:47                         ` Jean-Philippe Brucker
     [not found]                           ` <fea420ff-e738-e2ed-ab1e-a3f4dde4b6ef-5wv7dgnIgG8@public.gmane.org>
2018-05-26  3:53                             ` Xu Zaibo
     [not found]                               ` <5B08DA21.3070507-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-29 11:55                                 ` Jean-Philippe Brucker
     [not found]                                   ` <99ff4f89-86ef-a251-894c-8aa8a47d2a69-5wv7dgnIgG8@public.gmane.org>
2018-05-29 12:24                                     ` Xu Zaibo
2018-08-27  8:06       ` Xu Zaibo
     [not found]         ` <5B83B11E.7010807-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-08-31 13:34           ` Jean-Philippe Brucker
     [not found]             ` <1d5b6529-4e5a-723c-3f1b-dd5a9adb490c-5wv7dgnIgG8@public.gmane.org>
2018-09-01  2:23               ` Xu Zaibo
     [not found]                 ` <5B89F818.7060300-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-09-03 10:34                   ` Jean-Philippe Brucker
     [not found]                     ` <3a961aff-e830-64bb-b6a9-14e08de1abf5-5wv7dgnIgG8@public.gmane.org>
2018-09-04  2:12                       ` Xu Zaibo
     [not found]                         ` <5B8DEA15.7020404-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-09-04 10:57                           ` Jean-Philippe Brucker
     [not found]                             ` <bc27f902-4d12-21b7-b9e9-18bcae170503-5wv7dgnIgG8@public.gmane.org>
2018-09-05  3:15                               ` Xu Zaibo
     [not found]                                 ` <5B8F4A59.20004-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-09-05 11:02                                   ` Jean-Philippe Brucker
     [not found]                                     ` <b51107b8-a525-13ce-f4c3-d423b8502c27-5wv7dgnIgG8@public.gmane.org>
2018-09-06  7:26                                       ` Xu Zaibo
2018-05-11 19:06   ` [PATCH v2 14/40] dt-bindings: document stall and PASID properties for IOMMU masters Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 15/40] iommu/of: Add stall and pasid properties to iommu_fwspec Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 16/40] arm64: mm: Pin down ASIDs for sharing mm with devices Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-17-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-15 14:16       ` Catalin Marinas
     [not found]         ` <20180515141658.vivrgcyww2pxumye-+1aNUgJU5qkijLcmloz0ER/iLCjYCKR+VpNB7YpNyf8@public.gmane.org>
2018-05-17 10:01           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 17/40] iommu/arm-smmu-v3: Link domains and devices Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-18-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-17 16:07       ` Jonathan Cameron
     [not found]         ` <20180517170748.00004927-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:49           ` Jean-Philippe Brucker
2018-09-10 15:16       ` Auger Eric
2018-05-11 19:06   ` [PATCH v2 18/40] iommu/io-pgtable-arm: Factor out ARM LPAE register defines Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 19/40] iommu: Add generic PASID table library Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 20/40] iommu/arm-smmu-v3: Move context descriptor code Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 21/40] iommu/arm-smmu-v3: Add support for Substream IDs Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-22-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-31 11:01       ` Bharat Kumar Gogada
     [not found]         ` <BLUPR0201MB1505AA55707BE2E13392FFAFA5630-hRBPhS1iNj/g9tdZWAsUFxrHTHEw16jenBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2018-06-01 10:46           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 22/40] iommu/arm-smmu-v3: Add second level of context descriptor table Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 23/40] iommu/arm-smmu-v3: Share process page tables Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 24/40] iommu/arm-smmu-v3: Seize private ASID Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 25/40] iommu/arm-smmu-v3: Add support for VHE Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 26/40] iommu/arm-smmu-v3: Enable broadcast TLB maintenance Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 27/40] iommu/arm-smmu-v3: Add SVA feature checking Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 28/40] iommu/arm-smmu-v3: Implement mm operations Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 29/40] iommu/arm-smmu-v3: Add support for Hardware Translation Table Update Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 30/40] iommu/arm-smmu-v3: Register I/O Page Fault queue Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 31/40] iommu/arm-smmu-v3: Improve add_device error handling Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 32/40] iommu/arm-smmu-v3: Maintain a SID->device structure Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 33/40] iommu/arm-smmu-v3: Add stall support for platform devices Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 34/40] ACPI/IORT: Check ATS capability in root complex nodes Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 35/40] iommu/arm-smmu-v3: Add support for PCI ATS Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-36-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-19 17:25       ` Sinan Kaya
     [not found]         ` <922474e8-0aa5-e022-0502-f1e51b0d4859-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-05-21 14:52           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 36/40] iommu/arm-smmu-v3: Hook up ATC invalidation to mm ops Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 37/40] iommu/arm-smmu-v3: Disable tagged pointers Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 38/40] PCI: Make "PRG Response PASID Required" handling common Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 39/40] iommu/arm-smmu-v3: Add support for PRI Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-40-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-25 14:08       ` Bharat Kumar Gogada
     [not found]         ` <BLUPR0201MB150513BBAA161355DE9B3A48A5690-hRBPhS1iNj/g9tdZWAsUFxrHTHEw16jenBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2018-05-29 10:27           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 40/40] iommu/arm-smmu-v3: Add support for PCI PASID Jean-Philippe Brucker

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