From: Will Deacon <will@kernel.org>
To: joro@8bytes.org
Cc: jean-philippe@linaro.org, iommu@lists.linux-foundation.org,
robin.murphy@arm.com
Subject: [GIT PULL] iommu/arm-smmu: Big batch of updates for 5.4
Date: Fri, 23 Aug 2019 15:54:41 +0100 [thread overview]
Message-ID: <20190823145440.2b7ejsnglz2bju5k@willie-the-truck> (raw)
Hi Joerg,
Please pull these ARM SMMU updates for 5.4. The branch is based on the
for-joerg/batched-unmap branch that you pulled into iommu/core already
because I didn't want to rebase everything onto -rc3. The pull request
was generated against iommu/core.
There's a lot of code here, but the headlines are:
* Complete refactoring of arm-smmu.c to allow for implementation-specific
quirks, errata and general weirdness outside of the core architecture
support code.
* Rework of the SMMUv3 ATS support, after it was found to be broken.
Since it's a pretty niche thing for us right now, the support is
effectively reverted for -stable kernels.
* New algorithm for submitting commands to the SMMUv3 command queue
which removes the need for a spinlock and reduces CPU usage under
heavy I/O loads.
There's some ongoing work to extend io-pgtable to be able to deal with
high virtual address ranges but that's not quite there yet and I hope
to queue it for 5.5 instead.
Any problems, just shout (although it's a public holiday on Monday in
the UK, so you'll have to shout very loudly indeed).
Cheers,
Will
--->8
The following changes since commit 3951c41af4a65ba418e6b1b973d398552bedb84f:
iommu/io-pgtable: Pass struct iommu_iotlb_gather to ->tlb_add_page() (2019-07-29 17:22:59 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git for-joerg/arm-smmu/updates
for you to fetch changes up to 1554240ff864da9eb99e2233d3faf191c567c47a:
Merge branches 'for-joerg/arm-smmu/smmu-v2' and 'for-joerg/arm-smmu/smmu-v3' into for-joerg/arm-smmu/updates (2019-08-23 15:05:45 +0100)
----------------------------------------------------------------
Robin Murphy (18):
iommu/arm-smmu: Mask TLBI address correctly
iommu/qcom: Mask TLBI addresses correctly
iommu/arm-smmu: Convert GR0 registers to bitfields
iommu/arm-smmu: Convert GR1 registers to bitfields
iommu/arm-smmu: Convert context bank registers to bitfields
iommu/arm-smmu: Rework cb_base handling
iommu/arm-smmu: Split arm_smmu_tlb_inv_range_nosync()
iommu/arm-smmu: Get rid of weird "atomic" write
iommu/arm-smmu: Abstract GR1 accesses
iommu/arm-smmu: Abstract context bank accesses
iommu/arm-smmu: Abstract GR0 accesses
iommu/arm-smmu: Rename arm-smmu-regs.h
iommu/arm-smmu: Add implementation infrastructure
iommu/arm-smmu: Move Secure access quirk to implementation
iommu/arm-smmu: Add configuration implementation hook
iommu/arm-smmu: Add reset implementation hook
iommu/arm-smmu: Add context init implementation hook
iommu/arm-smmu: Ensure 64-bit I/O accessors are available on 32-bit CPU
Will Deacon (16):
iommu/arm-smmu-v3: Separate s/w and h/w views of prod and cons indexes
iommu/arm-smmu-v3: Drop unused 'q' argument from Q_OVF macro
iommu/arm-smmu-v3: Move low-level queue fields out of arm_smmu_queue
iommu/arm-smmu-v3: Operate directly on low-level queue where possible
iommu/arm-smmu-v3: Reduce contention during command-queue insertion
iommu/arm-smmu-v3: Defer TLB invalidation until ->iotlb_sync()
iommu/arm-smmu: Make private implementation details static
iommu/arm-smmu-v3: Document ordering guarantees of command insertion
iommu/arm-smmu-v3: Disable detection of ATS and PRI
iommu/arm-smmu-v3: Remove boolean bitfield for 'ats_enabled' flag
iommu/arm-smmu-v3: Don't issue CMD_SYNC for zero-length invalidations
iommu/arm-smmu-v3: Rework enabling/disabling of ATS for PCI masters
iommu/arm-smmu-v3: Fix ATC invalidation ordering wrt main TLBs
iommu/arm-smmu-v3: Avoid locking on invalidation path when not using ATS
Revert "iommu/arm-smmu-v3: Disable detection of ATS and PRI"
Merge branches 'for-joerg/arm-smmu/smmu-v2' and 'for-joerg/arm-smmu/smmu-v3' into for-joerg/arm-smmu/updates
MAINTAINERS | 3 +-
drivers/iommu/Makefile | 2 +-
drivers/iommu/arm-smmu-impl.c | 174 ++++++++
drivers/iommu/arm-smmu-regs.h | 210 ----------
drivers/iommu/arm-smmu-v3.c | 945 +++++++++++++++++++++++++++++++-----------
drivers/iommu/arm-smmu.c | 579 ++++++++------------------
drivers/iommu/arm-smmu.h | 402 ++++++++++++++++++
drivers/iommu/qcom_iommu.c | 17 +-
8 files changed, 1482 insertions(+), 850 deletions(-)
create mode 100644 drivers/iommu/arm-smmu-impl.c
delete mode 100644 drivers/iommu/arm-smmu-regs.h
create mode 100644 drivers/iommu/arm-smmu.h
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
next reply other threads:[~2019-08-23 14:55 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 14:54 Will Deacon [this message]
2019-08-28 21:42 ` [GIT PULL] iommu/arm-smmu: Big batch of updates for 5.4 Will Deacon
2019-08-30 10:29 ` Joerg Roedel
2019-08-30 11:24 ` Will Deacon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190823145440.2b7ejsnglz2bju5k@willie-the-truck \
--to=will@kernel.org \
--cc=iommu@lists.linux-foundation.org \
--cc=jean-philippe@linaro.org \
--cc=joro@8bytes.org \
--cc=robin.murphy@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).