From: Simon Horman <horms@verge.net.au>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: linux-renesas-soc@vger.kernel.org,
Magnus Damm <damm+renesas@opensource.se>,
iommu@lists.linux-foundation.org
Subject: Re: [PATCH 1/2] iommu/ipmmu-vmsa: Move IMTTBCR_SL0_TWOBIT_* to restore sort order
Date: Thu, 5 Sep 2019 10:44:43 +0200 [thread overview]
Message-ID: <20190905084443.z55xbhijq5ekhkpn@verge.net.au> (raw)
In-Reply-To: <20190904120802.2163-2-geert+renesas@glider.be>
On Wed, Sep 04, 2019 at 02:08:01PM +0200, Geert Uytterhoeven wrote:
> Move the recently added IMTTBCR_SL0_TWOBIT_* definitions up, to make
> sure all IMTTBCR register bit definitions are sorted by decreasing bit
> index. Add comments to make it clear that they exist on R-Car Gen3
> only.
>
> Fixes: c295f504fb5a38ab ("iommu/ipmmu-vmsa: Allow two bit SL0")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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next prev parent reply other threads:[~2019-09-05 8:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-04 12:08 [PATCH 0/2] iommu/ipmmu-vmsa: Disable cache snoop transactions on R-Car Gen3 Geert Uytterhoeven
2019-09-04 12:08 ` [PATCH 1/2] iommu/ipmmu-vmsa: Move IMTTBCR_SL0_TWOBIT_* to restore sort order Geert Uytterhoeven
2019-09-05 8:44 ` Simon Horman [this message]
2019-09-04 12:08 ` [PATCH 2/2] iommu/ipmmu-vmsa: Disable cache snoop transactions on R-Car Gen3 Geert Uytterhoeven
2019-09-05 8:44 ` Simon Horman
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