From: kholk11@gmail.com
To: linux-arm-msm@vger.kernel.org
Cc: marijns95@gmail.com, iommu@lists.linux-foundation.org,
agross@kernel.org, kholk11@gmail.com
Subject: [PATCH v4 4/7] iommu/qcom: Properly reset the IOMMU context
Date: Wed, 2 Oct 2019 00:02:02 +0200 [thread overview]
Message-ID: <20191001220205.6423-5-kholk11@gmail.com> (raw)
In-Reply-To: <20191001220205.6423-1-kholk11@gmail.com>
From: AngeloGioacchino Del Regno <kholk11@gmail.com>
To avoid context faults reset the context entirely on detach and
to ensure a fresh clean start also do a complete reset before
programming the context for domain initialization.
Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
---
drivers/iommu/qcom_iommu.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
index c8957ec83b92..b4a38ef129e3 100644
--- a/drivers/iommu/qcom_iommu.c
+++ b/drivers/iommu/qcom_iommu.c
@@ -220,6 +220,23 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
return IRQ_HANDLED;
}
+static void qcom_iommu_reset_ctx(struct qcom_iommu_ctx *ctx)
+{
+ iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_FSR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_PAR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_TCR2, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_TCR, 0);
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, 0);
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
+
+ /* Should we issue a TLBSYNC there instead? */
+ mb();
+}
+
static int qcom_iommu_init_domain(struct iommu_domain *domain,
struct qcom_iommu_dev *qcom_iommu,
struct iommu_fwspec *fwspec)
@@ -267,6 +284,8 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
ctx->secure_init = true;
}
+ qcom_iommu_reset_ctx(ctx);
+
/* TCR */
iommu_writel(ctx, ARM_SMMU_CB_TCR2,
(pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
@@ -412,8 +431,8 @@ static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *de
for (i = 0; i < fwspec->num_ids; i++) {
struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
- /* Disable the context bank: */
- iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
+ /* Disable and reset the context bank */
+ qcom_iommu_reset_ctx(ctx);
ctx->domain = NULL;
}
--
2.21.0
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next prev parent reply other threads:[~2019-10-01 22:02 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-01 22:01 [PATCH v4 0/7] Add support for QCOM IOMMU v2 and 500 kholk11
2019-10-01 22:01 ` [PATCH v4 1/7] firmware: qcom: scm: Add function to set IOMMU pagetable addressing kholk11
2019-10-15 11:14 ` Joerg Roedel
2019-10-15 12:33 ` AngeloGioacchino Del Regno
2019-10-15 12:40 ` Joerg Roedel
2019-10-15 13:09 ` AngeloGioacchino Del Regno
2019-10-01 22:02 ` [PATCH v4 2/7] iommu/qcom: Use the asid read from device-tree if specified kholk11
2019-10-15 12:09 ` Robin Murphy
2019-10-15 13:06 ` AngeloGioacchino Del Regno
2019-10-01 22:02 ` [PATCH v4 3/7] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior kholk11
2019-10-01 22:02 ` kholk11 [this message]
2019-10-02 11:29 ` [PATCH v4 4/7] iommu/qcom: Properly reset the IOMMU context Robin Murphy
2019-10-01 22:02 ` [PATCH v4 5/7] iommu/qcom: Add support for AArch64 IOMMU pagetables kholk11
2019-10-01 22:02 ` [PATCH v4 6/7] iommu/qcom: Index contexts by asid number to allow asid 0 kholk11
2019-10-01 22:02 ` [PATCH v4 7/7] iommu/qcom: Add support for QCIOMMUv2 and QCIOMMU-500 secured contexts kholk11
2019-10-05 4:56 ` [PATCH v4 0/7] Add support for QCOM IOMMU v2 and 500 Bjorn Andersson
2019-10-05 9:32 ` AngeloGioacchino Del Regno
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