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From: Will Deacon <will@kernel.org>
To: Yong Wu <yong.wu@mediatek.com>
Cc: youlin.pei@mediatek.com, anan.sun@mediatek.com,
	Nicolas Boichat <drinkcat@chromium.org>,
	cui.zhang@mediatek.com, srv_heupstream@mediatek.com,
	chao.hao@mediatek.com, Will Deacon <will.deacon@arm.com>,
	linux-kernel@vger.kernel.org, Evan Green <evgreen@chromium.org>,
	Tomasz Figa <tfiga@google.com>,
	iommu@lists.linux-foundation.org,
	linux-mediatek@lists.infradead.org,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Robin Murphy <robin.murphy@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 3/4] iommu/mediatek: Use writel for TLB range invalidation
Date: Mon, 14 Oct 2019 22:11:14 +0100
Message-ID: <20191014211113.jq5qwe5pfonyocr3@willie-the-truck> (raw)
In-Reply-To: <1570861427.19130.65.camel@mhfsdcap03>

On Sat, Oct 12, 2019 at 02:23:47PM +0800, Yong Wu wrote:
> On Fri, 2019-10-11 at 17:29 +0100, Will Deacon wrote:
> > On Wed, Oct 09, 2019 at 09:19:02PM +0800, Yong Wu wrote:
> > > Use writel for the register F_MMU_INV_RANGE which is for triggering the
> > > HW work. We expect all the setting(iova_start/iova_end...) have already
> > > been finished before F_MMU_INV_RANGE.
> > > 
> > > Signed-off-by: Anan.Sun <anan.sun@mediatek.com>
> > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > ---
> > > This is a improvement rather than fixing a issue.
> > > ---
> > >  drivers/iommu/mtk_iommu.c | 3 +--
> > >  1 file changed, 1 insertion(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > > index 24a13a6..607f92c 100644
> > > --- a/drivers/iommu/mtk_iommu.c
> > > +++ b/drivers/iommu/mtk_iommu.c
> > > @@ -187,8 +187,7 @@ static void mtk_iommu_tlb_add_flush(unsigned long iova, size_t size,
> > >  		writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
> > >  		writel_relaxed(iova + size - 1,
> > >  			       data->base + REG_MMU_INVLD_END_A);
> > > -		writel_relaxed(F_MMU_INV_RANGE,
> > > -			       data->base + REG_MMU_INVALIDATE);
> > > +		writel(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
> > 
> > I don't understand this change.
> > 
> > Why is it an "improvement" and which accesses are you ordering with the
> > writel?
> 
> The register(F_MMU_INV_RANGE) will trigger HW to begin flush range. HW
> expect the other register iova_start/end/flush_type always is ready
> before trigger. thus I'd like use writel to guarantee the previous
> register has been finished.

Given that these are all MMIO writes to the same device, then
writel_relaxed() should give you the ordering you need. If you look at
memory_barriers.txt, it says:

  | they [readX_relaxed() and writeX_relaxed()] are still guaranteed to
  | be ordered with respect to other accesses from the same CPU thread
  | to the same peripheral when operating on __iomem pointers mapped
  | with the default I/O attributes.

> I didn't see the writel_relaxed cause some error in practice, we only
> think writel is necessary here in theory. so call it "improvement".

Ok, but I don't think it's needed in this case.

Will
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Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-09 13:19 [PATCH v2 1/4] iommu/mediatek: Correct the flush_iotlb_all callback Yong Wu
2019-10-09 13:19 ` [PATCH v2 2/4] iommu/mediatek: Move the tlb_sync into tlb_flush Yong Wu
2019-10-09 13:19 ` [PATCH v2 3/4] iommu/mediatek: Use writel for TLB range invalidation Yong Wu
2019-10-11 16:29   ` Will Deacon
2019-10-12  6:23     ` Yong Wu
2019-10-14 21:11       ` Will Deacon [this message]
2019-10-15  1:51         ` Yong Wu
2019-10-09 13:19 ` [PATCH v2 4/4] iommu/mediatek: Reduce the tlb flush timeout value Yong Wu

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