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From: Jacob Pan <jacob.jun.pan@linux.intel.com>
To: Lu Baolu <baolu.lu@linux.intel.com>
Cc: kevin.tian@intel.com, ashok.raj@intel.com,
	linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH 4/5] iommu/vt-d: Consolidate pasid-based tlb invalidation
Date: Tue, 3 Dec 2019 09:43:08 -0800
Message-ID: <20191203094308.60e348df@jacob-builder> (raw)
In-Reply-To: <20191122030449.28892-5-baolu.lu@linux.intel.com>

On Fri, 22 Nov 2019 11:04:48 +0800
Lu Baolu <baolu.lu@linux.intel.com> wrote:

> Merge pasid-based tlb invalidation into iommu->flush.p_iotlb_inv.
> 
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> ---
>  drivers/iommu/intel-iommu.c | 43
> +++++++++++++++++++++++++++++++++++++ drivers/iommu/intel-pasid.c |
> 18 ++-------------- drivers/iommu/intel-svm.c   | 23
> +++----------------- 3 files changed, 48 insertions(+), 36
> deletions(-)
> 
> diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
> index 4eeb18942d3c..fec78cc877c1 100644
> --- a/drivers/iommu/intel-iommu.c
> +++ b/drivers/iommu/intel-iommu.c
> @@ -3032,6 +3032,48 @@ qi_flush_dev_iotlb(struct intel_iommu *iommu,
> u16 sid, u16 pfsid, qi_submit_sync(&desc, iommu);
>  }
>  
> +/* PASID-based IOTLB invalidation */
> +static void
> +qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64
> addr,
> +		unsigned long npages, bool ih)
> +{
> +	struct qi_desc desc = {.qw2 = 0, .qw3 = 0};
> +
> +	/*
> +	 * npages == -1 means a PASID-selective invalidation,
> otherwise,
> +	 * a positive value for Page-selective-within-PASID
> invalidation.
> +	 * 0 is not a valid input.
> +	 */
> +	if (WARN_ON(!npages)) {
> +		pr_err("Invalid input npages = %ld\n", npages);
> +		return;
> +	}
> +
> +	if (npages == -1) {
> +		desc.qw0 = QI_EIOTLB_PASID(pasid) |
> +				QI_EIOTLB_DID(did) |
> +				QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
> +				QI_EIOTLB_TYPE;
> +		desc.qw1 = 0;
Is this based on the latest kernel? seems to be missing the recent
change for checking page selective cap. So I run into conflict.

+       /*                                                                     
+        * Do PASID granu IOTLB invalidation if page selective
  capability is   
+        * not
  available.                                                      
+
  */                                                                    
+       if (pages == -1 || !cap_pgsel_inv(svm->iommu->cap))
  {                  
+               desc.qw0 = QI_EIOTLB_PASID(svm->pasid)
  |                       

Seems missing this one in your base?

Refs: v5.3-rc6-2-g8744daf4b069                              
Author:     Jacob Pan <jacob.jun.pan@linux.intel.com>       
AuthorDate: Mon Aug 26 08:53:29 2019 -0700                  
Commit:     Joerg Roedel <jroedel@suse.de>                  
CommitDate: Tue Sep 3 15:01:27 2019 +0200                   
                                                            
    iommu/vt-d: Remove global page flush support            

> +	} else {
> +		int mask = ilog2(__roundup_pow_of_two(npages));
> +		unsigned long align = (1ULL << (VTD_PAGE_SHIFT +
> mask)); +
> +		if (WARN_ON_ONCE(!ALIGN(addr, align)))
> +			addr &= ~(align - 1);
> +
> +		desc.qw0 = QI_EIOTLB_PASID(pasid) |
> +				QI_EIOTLB_DID(did) |
> +				QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
> +				QI_EIOTLB_TYPE;
> +		desc.qw1 = QI_EIOTLB_ADDR(addr) |
> +				QI_EIOTLB_IH(ih) |
> +				QI_EIOTLB_AM(mask);
> +	}
> +
> +	qi_submit_sync(&desc, iommu);
> +}
> +
>  static void intel_iommu_init_qi(struct intel_iommu *iommu)
>  {
>  	/*
> @@ -3065,6 +3107,7 @@ static void intel_iommu_init_qi(struct
> intel_iommu *iommu) iommu->flush.iotlb_inv = qi_flush_iotlb;
>  		iommu->flush.pc_inv = qi_flush_pasid;
>  		iommu->flush.dev_tlb_inv = qi_flush_dev_iotlb;
> +		iommu->flush.p_iotlb_inv = qi_flush_piotlb;
>  		pr_info("%s: Using Queued invalidation\n",
> iommu->name); }
>  }
> diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
> index 01dd9c86178b..78ff4eee8595 100644
> --- a/drivers/iommu/intel-pasid.c
> +++ b/drivers/iommu/intel-pasid.c
> @@ -359,20 +359,6 @@ pasid_set_flpm(struct pasid_entry *pe, u64 value)
>  	pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2);
>  }
>  
> -static void
> -iotlb_invalidation_with_pasid(struct intel_iommu *iommu, u16 did,
> u32 pasid) -{
> -	struct qi_desc desc;
> -
> -	desc.qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
> -			QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
> QI_EIOTLB_TYPE;
> -	desc.qw1 = 0;
> -	desc.qw2 = 0;
> -	desc.qw3 = 0;
> -
> -	qi_submit_sync(&desc, iommu);
> -}
> -
>  static void
>  devtlb_invalidation_with_pasid(struct intel_iommu *iommu,
>  			       struct device *dev, int pasid)
> @@ -409,7 +395,7 @@ void intel_pasid_tear_down_entry(struct
> intel_iommu *iommu, clflush_cache_range(pte, sizeof(*pte));
>  
>  	iommu->flush.pc_inv(iommu, did, pasid, QI_PC_GRAN_PSWD);
> -	iotlb_invalidation_with_pasid(iommu, did, pasid);
> +	iommu->flush.p_iotlb_inv(iommu, did, pasid, 0, -1, 0);
>  
>  	/* Device IOTLB doesn't need to be flushed in caching mode.
> */ if (!cap_caching_mode(iommu->cap))
> @@ -425,7 +411,7 @@ static void pasid_flush_caches(struct intel_iommu
> *iommu, 
>  	if (cap_caching_mode(iommu->cap)) {
>  		iommu->flush.pc_inv(iommu, did, pasid,
> QI_PC_GRAN_PSWD);
> -		iotlb_invalidation_with_pasid(iommu, did, pasid);
> +		iommu->flush.p_iotlb_inv(iommu, did, pasid, 0, -1,
> 0); } else {
>  		iommu_flush_write_buffer(iommu);
>  	}
> diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
> index f5594b9981a5..02c6b14f0568 100644
> --- a/drivers/iommu/intel-svm.c
> +++ b/drivers/iommu/intel-svm.c
> @@ -118,27 +118,10 @@ static void intel_flush_svm_range_dev (struct
> intel_svm *svm, struct intel_svm_d unsigned long address, unsigned
> long pages, int ih) {
>  	struct qi_desc desc;
> +	struct intel_iommu *iommu = svm->iommu;
>  
> -	if (pages == -1) {
> -		desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
> -			QI_EIOTLB_DID(sdev->did) |
> -			QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
> -			QI_EIOTLB_TYPE;
> -		desc.qw1 = 0;
> -	} else {
> -		int mask = ilog2(__roundup_pow_of_two(pages));
> -
> -		desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
> -				QI_EIOTLB_DID(sdev->did) |
> -				QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
> -				QI_EIOTLB_TYPE;
> -		desc.qw1 = QI_EIOTLB_ADDR(address) |
> -				QI_EIOTLB_IH(ih) |
> -				QI_EIOTLB_AM(mask);
> -	}
> -	desc.qw2 = 0;
> -	desc.qw3 = 0;
> -	qi_submit_sync(&desc, svm->iommu);
> +	iommu->flush.p_iotlb_inv(iommu, sdev->did,
> +				 svm->pasid, address, pages, ih);
>  
>  	if (sdev->dev_iotlb) {
>  		desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) |

[Jacob Pan]
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

  reply index

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-22  3:04 [PATCH 0/5] iommu/vt-d: Consolidate various cache flush ops Lu Baolu
2019-11-22  3:04 ` [PATCH 1/5] iommu/vt-d: Extend iommu_flush for scalable mode Lu Baolu
2019-11-22  3:04 ` [PATCH 2/5] iommu/vt-d: Consolidate pasid cache invalidation Lu Baolu
2019-11-22  3:04 ` [PATCH 3/5] iommu/vt-d: Consolidate device tlb invalidation Lu Baolu
2019-11-22  3:04 ` [PATCH 4/5] iommu/vt-d: Consolidate pasid-based " Lu Baolu
2019-12-03 17:43   ` Jacob Pan [this message]
2019-11-22  3:04 ` [PATCH 5/5] iommu/vt-d: Consolidate pasid-based device " Lu Baolu
2019-12-02 20:02 ` [PATCH 0/5] iommu/vt-d: Consolidate various cache flush ops Jacob Pan
2019-12-03  2:44   ` Lu Baolu
2019-12-03 16:50     ` Jacob Pan
2019-12-04  0:32       ` Lu Baolu
2019-12-04 17:41         ` Jacob Pan
2019-12-03  8:49 ` David Woodhouse
2019-12-04  0:27   ` Lu Baolu

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