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From: Jean-Philippe Brucker <jean-philippe@linaro.org>
To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-acpi@vger.kernel.org, devicetree@vger.kernel.org,
	iommu@lists.linux-foundation.org, will@kernel.org
Cc: mark.rutland@arm.com, guohanjun@huawei.com, rjw@rjwysocki.net,
	robh+dt@kernel.org, sudeep.holla@arm.com, bhelgaas@google.com,
	zhangfei.gao@linaro.org, robin.murphy@arm.com, lenb@kernel.org
Subject: [PATCH v5 09/13] iommu/arm-smmu-v3: Prepare for handling arm_smmu_write_ctx_desc() failure
Date: Wed, 15 Jan 2020 13:52:35 +0100	[thread overview]
Message-ID: <20200115125239.136759-10-jean-philippe@linaro.org> (raw)
In-Reply-To: <20200115125239.136759-1-jean-philippe@linaro.org>

Second-level context descriptor tables will be allocated lazily in
arm_smmu_write_ctx_desc(). Help with handling allocation failure by
moving the CD write into arm_smmu_domain_finalise_s1().

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
---
 drivers/iommu/arm-smmu-v3.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 7b7dea596f60..c35863073ab3 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -2299,8 +2299,15 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
 	cfg->cd.ttbr	= pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
 	cfg->cd.tcr	= pgtbl_cfg->arm_lpae_s1_cfg.tcr;
 	cfg->cd.mair	= pgtbl_cfg->arm_lpae_s1_cfg.mair;
+
+	ret = arm_smmu_write_ctx_desc(smmu_domain, 0, &cfg->cd);
+	if (ret)
+		goto out_free_cd_tables;
+
 	return 0;
 
+out_free_cd_tables:
+	arm_smmu_free_cd_tables(smmu_domain);
 out_free_asid:
 	arm_smmu_bitmap_free(smmu->asid_map, asid);
 	return ret;
@@ -2567,10 +2574,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
 	if (smmu_domain->stage != ARM_SMMU_DOMAIN_BYPASS)
 		master->ats_enabled = arm_smmu_ats_supported(master);
 
-	if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1)
-		arm_smmu_write_ctx_desc(smmu_domain, 0,
-					&smmu_domain->s1_cfg.cd);
-
 	arm_smmu_install_ste_for_dev(master);
 
 	spin_lock_irqsave(&smmu_domain->devices_lock, flags);
-- 
2.24.1

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  parent reply	other threads:[~2020-01-15 12:53 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-15 12:52 [PATCH v5 00/13] iommu: Add PASID support to Arm SMMUv3 Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 01/13] iommu/arm-smmu-v3: Drop __GFP_ZERO flag from DMA allocation Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 02/13] dt-bindings: document PASID property for IOMMU masters Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 03/13] iommu/arm-smmu-v3: Parse PASID devicetree property of platform devices Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 04/13] ACPI/IORT: Parse SSID property of named component node Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 05/13] iommu/arm-smmu-v3: Prepare arm_smmu_s1_cfg for SSID support Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 06/13] iommu/arm-smmu-v3: Add context descriptor tables allocators Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 07/13] iommu/arm-smmu-v3: Add support for Substream IDs Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 08/13] iommu/arm-smmu-v3: Propagate ssid_bits Jean-Philippe Brucker
2020-01-15 12:52 ` Jean-Philippe Brucker [this message]
2020-01-15 12:52 ` [PATCH v5 10/13] iommu/arm-smmu-v3: Add second level of context descriptor table Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 11/13] iommu/arm-smmu-v3: Improve add_device() error handling Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 12/13] PCI/ATS: Add PASID stubs Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 13/13] iommu/arm-smmu-v3: Add support for PCI PASID Jean-Philippe Brucker
2020-01-15 16:42 ` [PATCH v5 00/13] iommu: Add PASID support to Arm SMMUv3 Will Deacon
2020-01-15 18:29   ` Jean-Philippe Brucker

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