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Thu, 13 Feb 2020 08:52:03 -0800 (PST) From: Jean-Philippe Brucker To: bhelgaas@google.com, will@kernel.org, robh+dt@kernel.org, lorenzo.pieralisi@arm.com, joro@8bytes.org, baolu.lu@linux.intel.com, linux-doc@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org Subject: [PATCH 00/10] PCI/ATS: Device-tree support and other improvements Date: Thu, 13 Feb 2020 17:50:38 +0100 Message-Id: <20200213165049.508908-1-jean-philippe@linaro.org> X-Mailer: git-send-email 2.25.0 MIME-Version: 1.0 Cc: mark.rutland@arm.com, frowand.list@gmail.com, corbet@lwn.net, liviu.dudau@arm.com, sudeep.holla@arm.com, rjw@rjwysocki.net, guohanjun@huawei.com, amurray@thegoodpenguin.co.uk, robin.murphy@arm.com, dwmw2@infradead.org, lenb@kernel.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Enable ATS on device-tree based systems, and factor the common ATS enablement checks into pci_enable_ats(). ATS support in PCIe endpoints is discovered through the ATS capability, but there is no common method for discovering whether the host bridge supports ATS. Each vendor provides their own ACPI method: * DMAR (Intel) reports ATS support per domain or per root port. * IVRS (AMD) reports negative ATS support for a range of devices. * IORT (ARM) reports ATS support for a root complex. In my opinion it's important that we only enable ATS if the host bridge supports it, but I don't think a finer granularity is useful. If the host bridge ignores the Address Translation field of TLP headers, it could in theory treat a Translation Request as a Memory Read Request, and a Translated Request as a normal memory access, which could result in silent memory corruption. Patches 1-3 add a device-tree property that declares ATS support in host controllers. We only add it to the generic host, but the property can easily be reused by other PCI hosts. Alternatively, the host drivers can directly set the new ats_supported property of the host bridge introduced in patch 1. Patch 4 uses the new ats_supported host bridge property for IORT. Patch 9 removes the old method that set a flag in each endpoint's fwspec. Patches 5-8 put all checks required for enabling ATS in common, along with the new host bridge check. Jean-Philippe Brucker (11): dt-bindings: PCI: generic: Add ats-supported property PCI: Add ats_supported host bridge flag PCI: OF: Check whether the host bridge supports ATS ACPI/IORT: Check ATS capability in root complex node PCI/ATS: Gather checks into pci_ats_supported() iommu/amd: Use pci_ats_supported() iommu/arm-smmu-v3: Use pci_ats_supported() iommu/vt-d: Use pci_ats_supported() ACPI/IORT: Drop ATS fwspec flag arm64: dts: fast models: Enable PCIe ATS for Base RevC FVP Documentation: Generalize the "pci=noats" boot parameter .../admin-guide/kernel-parameters.txt | 4 +- .../bindings/pci/host-generic-pci.yaml | 6 +++ arch/arm64/boot/dts/arm/fvp-base-revc.dts | 1 + drivers/acpi/arm64/iort.c | 38 +++++++++++++------ drivers/acpi/pci_root.c | 3 ++ drivers/iommu/amd_iommu.c | 12 ++---- drivers/iommu/arm-smmu-v3.c | 18 ++------- drivers/iommu/intel-iommu.c | 9 ++--- drivers/pci/ats.c | 30 ++++++++++++++- drivers/pci/controller/pci-host-common.c | 1 + drivers/pci/of.c | 9 +++++ drivers/pci/probe.c | 7 ++++ include/linux/acpi_iort.h | 8 ++++ include/linux/iommu.h | 4 -- include/linux/of_pci.h | 3 ++ include/linux/pci-ats.h | 3 ++ include/linux/pci.h | 1 + 17 files changed, 110 insertions(+), 47 deletions(-) -- 2.25.0 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu