From: Joerg Roedel <joro@8bytes.org>
To: Adrian Huang <adrianhuang0701@gmail.com>
Cc: iommu@lists.linux-foundation.org, Adrian Huang <ahuang12@lenovo.com>
Subject: Re: [PATCH 1/1] iommu/amd: Fix the configuration of GCR3 table root pointer
Date: Wed, 19 Feb 2020 11:48:28 +0100 [thread overview]
Message-ID: <20200219104828.GE1961@8bytes.org> (raw)
In-Reply-To: <20200214104451.16076-1-ahuang12@lenovo.com>
On Fri, Feb 14, 2020 at 06:44:51PM +0800, Adrian Huang wrote:
> From: Adrian Huang <ahuang12@lenovo.com>
>
> The SPA of the GCR3 table root pointer[51:31] masks 20 bits. However,
> this requires 21 bits (Please see the AMD IOMMU specification).
> This leads to the potential failure when the bit 51 of SPA of
> the GCR3 table root pointer is 1'.
>
> Signed-off-by: Adrian Huang <ahuang12@lenovo.com>
Applied, thanks.
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prev parent reply other threads:[~2020-02-19 10:48 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 10:44 [PATCH 1/1] iommu/amd: Fix the configuration of GCR3 table root pointer Adrian Huang
2020-02-19 10:48 ` Joerg Roedel [this message]
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