From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DE60C433DF for ; Thu, 11 Jun 2020 22:37:16 +0000 (UTC) Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9941C206D7 for ; Thu, 11 Jun 2020 22:37:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="Dtbn4YRJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9941C206D7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=iommu-bounces@lists.linux-foundation.org Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 56B2C88652; Thu, 11 Jun 2020 22:37:15 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7El0X9zN80Uz; Thu, 11 Jun 2020 22:37:14 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [140.211.9.56]) by whitealder.osuosl.org (Postfix) with ESMTP id 98001885FA; Thu, 11 Jun 2020 22:37:14 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id 78CD6C0178; Thu, 11 Jun 2020 22:37:14 +0000 (UTC) Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) by lists.linuxfoundation.org (Postfix) with ESMTP id 04E29C016F for ; Thu, 11 Jun 2020 22:37:13 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id E120C876FC for ; Thu, 11 Jun 2020 22:37:12 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ptBSNzdQZKYK for ; Thu, 11 Jun 2020 22:37:12 +0000 (UTC) X-Greylist: from auto-whitelisted by SQLgrey-1.7.6 Received: from m43-7.mailgun.net (m43-7.mailgun.net [69.72.43.7]) by fraxinus.osuosl.org (Postfix) with ESMTPS id 718E98767C for ; Thu, 11 Jun 2020 22:37:09 +0000 (UTC) DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1591915032; h=Message-Id: Date: Subject: Cc: To: From: Sender; bh=6xUaMfKJXxXcIBGJIgKiTLhHa7NBz100vUpvyY8Yq5A=; b=Dtbn4YRJAv1aXA6Yl+QVDFsYDOYfY2umuht+TAUEloBO2K0LyZdmVl6Zb3nbCxNvdtgQjXwW af0Gzku4E436aoMYVmz3sGqFJ8fiyPBt/zBRTbivahuJIjXKypZajF3LM+cvg8q1lol3BFHE HdSLxpTFkmLQtsK+BXLMpHpIINg= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI3NDkwMCIsICJpb21tdUBsaXN0cy5saW51eC1mb3VuZGF0aW9uLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-east-1.postgun.com with SMTP id 5ee2b2108fe116ddd99d1173 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 11 Jun 2020 22:37:04 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 7CA9EC43395; Thu, 11 Jun 2020 22:37:03 +0000 (UTC) Received: from jordan-laptop.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id B01C4C433C8; Thu, 11 Jun 2020 22:37:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B01C4C433C8 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: linux-arm-msm@vger.kernel.org Subject: [PATCH] iommu/arm-smmu: Add a init_context_bank implementation hook Date: Thu, 11 Jun 2020 16:36:56 -0600 Message-Id: <20200611223656.4724-1-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.17.1 Cc: freedreno@lists.freedesktop.org, Robin Murphy , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Will Deacon , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Add a new implementation hook to allow the implementation specific code to tweek the context bank configuration just before it gets written. The first user will be the Adreno GPU implementation to turn on SCTLR.HUPCF to ensure that a page fault doesn't terminating pending transactions. Doing so could hang the GPU if one of the terminated transactions is a CP read. This depends on the arm-smmu adreno SMMU implementation [1]. [1] https://patchwork.kernel.org/patch/11600943/ Signed-off-by: Jordan Crouse --- drivers/iommu/arm-smmu-qcom.c | 13 +++++++++++++ drivers/iommu/arm-smmu.c | 28 +++++++++++++--------------- drivers/iommu/arm-smmu.h | 11 +++++++++++ 3 files changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c index 6d0ab4865fc7..e5c6345da6fc 100644 --- a/drivers/iommu/arm-smmu-qcom.c +++ b/drivers/iommu/arm-smmu-qcom.c @@ -17,6 +17,18 @@ static bool qcom_adreno_smmu_is_gpu_device(struct arm_smmu_domain *smmu_domain) return of_device_is_compatible(smmu_domain->dev.of_node, "qcom,adreno"); } +static void qcom_adreno_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_cb *cb) +{ + /* + * On the GPU device we want to process subsequent transactions after a + * fault to keep the GPU from hanging + */ + + if (qcom_adreno_smmu_is_gpu_device(smmu_domain)) + cb->sctlr |= ARM_SMMU_SCTLR_HUPCF; +} + static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg) { @@ -92,6 +104,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_impl = { .init_context = qcom_adreno_smmu_init_context, .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, + .init_context_bank = qcom_adreno_smmu_init_context_bank, }; diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index a06cbcaec247..f0f201ece3a0 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -86,13 +86,6 @@ struct arm_smmu_smr { bool valid; }; -struct arm_smmu_cb { - u64 ttbr[2]; - u32 tcr[2]; - u32 mair[2]; - struct arm_smmu_cfg *cfg; -}; - struct arm_smmu_master_cfg { struct arm_smmu_device *smmu; s16 smendx[]; @@ -579,6 +572,18 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair >> 32; } } + + cb->sctlr = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE | ARM_SMMU_SCTLR_AFE | + ARM_SMMU_SCTLR_TRE | ARM_SMMU_SCTLR_M; + + if (stage1) + cb->sctlr |= ARM_SMMU_SCTLR_S1_ASIDPNE; + if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) + cb->sctlr |= ARM_SMMU_SCTLR_E; + + /* Give the implementation a chance to adjust the configuration */ + if (smmu_domain->smmu->impl && smmu_domain->smmu->impl->init_context_bank) + smmu_domain->smmu->impl->init_context_bank(smmu_domain, cb); } static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) @@ -657,14 +662,7 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) } /* SCTLR */ - reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE | ARM_SMMU_SCTLR_AFE | - ARM_SMMU_SCTLR_TRE | ARM_SMMU_SCTLR_M; - if (stage1) - reg |= ARM_SMMU_SCTLR_S1_ASIDPNE; - if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) - reg |= ARM_SMMU_SCTLR_E; - - arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, cb->sctlr); } /* diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index 79d441024043..9b539820997b 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -142,6 +142,7 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_SCTLR 0x0 #define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12) +#define ARM_SMMU_SCTLR_HUPCF BIT(8) #define ARM_SMMU_SCTLR_CFCFG BIT(7) #define ARM_SMMU_SCTLR_CFIE BIT(6) #define ARM_SMMU_SCTLR_CFRE BIT(5) @@ -349,6 +350,14 @@ struct arm_smmu_domain { bool aux; }; +struct arm_smmu_cb { + u64 ttbr[2]; + u32 tcr[2]; + u32 mair[2]; + u32 sctlr; + struct arm_smmu_cfg *cfg; +}; + static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) { u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | @@ -403,6 +412,8 @@ struct arm_smmu_impl { void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync, int status); int (*def_domain_type)(struct device *dev); + void (*init_context_bank)(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_cb *cb); }; static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n) -- 2.17.1 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu