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From: Lu Baolu <>
To: Joerg Roedel <>
Subject: [PATCH 1/6] iommu/vt-d: Make Intel SVM code 64-bit only
Date: Tue, 23 Jun 2020 07:13:40 +0800	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

Current Intel SVM is designed by setting the pgd_t of the processor page
table to FLPTR field of the PASID entry. The first level translation only
supports 4 and 5 level paging structures, hence it's infeasible for the
IOMMU to share a processor's page table when it's running in 32-bit mode.
Let's disable 32bit support for now and claim support only when all the
missing pieces are ready in the future.

Fixes: 1c4f88b7f1f92 ("iommu/vt-d: Shared virtual address in scalable mode")
Suggested-by: Joerg Roedel <>
Signed-off-by: Lu Baolu <>
 drivers/iommu/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index b510f67dfa49..6dc49ed8377a 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -211,7 +211,7 @@ config INTEL_IOMMU_DEBUGFS
 	bool "Support for Shared Virtual Memory with Intel IOMMU"
-	depends on INTEL_IOMMU && X86
+	depends on INTEL_IOMMU && X86_64
 	select PCI_PASID
 	select PCI_PRI

iommu mailing list

  reply	other threads:[~2020-06-22 23:18 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-22 23:13 [PATCH 0/6] [PULL REQUEST] iommu/vt-d: fixes for v5.8 Lu Baolu
2020-06-22 23:13 ` Lu Baolu [this message]
2020-06-22 23:13 ` [PATCH 2/6] iommu/vt-d: Set U/S bit in first level page table by default Lu Baolu
2020-06-22 23:13 ` [PATCH 3/6] iommu/vt-d: Don't apply gfx quirks to untrusted devices Lu Baolu
2020-06-22 23:13 ` [PATCH 4/6] iommu/vt-d: Enable PCI ACS for platform opt in hint Lu Baolu
2020-06-22 23:13 ` [PATCH 5/6] iommu/vt-d: Update scalable mode paging structure coherency Lu Baolu
2020-06-22 23:13 ` [PATCH 6/6] iommu/vt-d: Fix misuse of iommu_domain_identity_map() Lu Baolu
2020-06-23  8:12 ` [PATCH 0/6] [PULL REQUEST] iommu/vt-d: fixes for v5.8 Joerg Roedel

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