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X-UUID: 01d10d02106b4869b5bee400eb664654-20200629 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 253034485; Mon, 29 Jun 2020 15:14:19 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 29 Jun 2020 15:14:16 +0800 Received: from localhost.localdomain (10.15.20.246) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 29 Jun 2020 15:14:16 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger Subject: [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register Date: Mon, 29 Jun 2020 15:13:04 +0800 Message-ID: <20200629071310.1557-5-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200629071310.1557-1-chao.hao@mediatek.com> References: <20200629071310.1557-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Cc: devicetree@vger.kernel.org, FY Yang , wsd_upstream@mediatek.com, linux-kernel@vger.kernel.org, Evan Green , Chao Hao , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition in MISC_CTRL register. F_MMU_STANDARD_AXI_MODE_BIT: If we set F_MMU_STANDARD_AXI_MODE_BIT(bit[3][19] = 0, not follow standard AXI protocol), iommu will send urgent read command firstly compare with normal read command to improve performance. F_MMU_IN_ORDER_WR_EN: If we set F_MMU_IN_ORDER_WR_EN(bit[1][17] = 0, out-of-order write), iommu will re-order write command and send more higher priority write command instead of sending write command in order. The feature be controlled by OUT_ORDER_EN macro definition. Cc: Matthias Brugger Suggested-by: Yong Wu Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 12 +++++++++++- drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 8f81df6cbe51..67b46b5d83d9 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -42,6 +42,9 @@ #define F_INVLD_EN1 BIT(1) #define REG_MMU_MISC_CTRL 0x048 +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) + #define REG_MMU_DCM_DIS 0x050 #define REG_MMU_CTRL_REG 0x110 @@ -574,10 +577,17 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) } writel_relaxed(0, data->base + REG_MMU_DCM_DIS); + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { /* The register is called STANDARD_AXI_MODE in this case */ - writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); + regval = 0; + } else { + /* For mm_iommu, it can improve performance by the setting */ + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; + if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_EN)) + regval &= ~F_MMU_IN_ORDER_WR_EN; } + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, dev_name(data->dev), (void *)data)) { diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 7cc39f729263..4b780b651ef4 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -22,6 +22,7 @@ #define HAS_BCLK BIT(1) #define HAS_VLD_PA_RNG BIT(2) #define RESET_AXI BIT(3) +#define OUT_ORDER_EN BIT(4) #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ ((((pdata)->flags) & (_x)) == (_x)) -- 2.18.0 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu