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From: Jacob Pan <jacob.jun.pan@linux.intel.com>
To: "Tian, Kevin" <kevin.tian@intel.com>
Cc: "Raj, Ashok" <ashok.raj@intel.com>,
	LKML <linux-kernel@vger.kernel.org>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH 3/7] iommu/vt-d: Fix PASID devTLB invalidation
Date: Mon, 29 Jun 2020 21:58:59 -0700	[thread overview]
Message-ID: <20200629215859.3ab77421@jacob-builder> (raw)
In-Reply-To: <MWHPR11MB1645B3CAC72D63AD535FD6DC8C6F0@MWHPR11MB1645.namprd11.prod.outlook.com>

On Tue, 30 Jun 2020 03:01:29 +0000
"Tian, Kevin" <kevin.tian@intel.com> wrote:

> > From: Lu Baolu <baolu.lu@linux.intel.com>
> > Sent: Thursday, June 25, 2020 3:26 PM
> > 
> > On 2020/6/23 23:43, Jacob Pan wrote:  
> > > DevTLB flush can be used for both DMA request with and without
> > > PASIDs. The former uses PASID#0 (RID2PASID), latter uses non-zero
> > > PASID for SVA usage.
> > >
> > > This patch adds a check for PASID value such that devTLB flush
> > > with PASID is used for SVA case. This is more efficient in that
> > > multiple PASIDs can be used by a single device, when tearing down
> > > a PASID entry we shall flush only the devTLB specific to a PASID.
> > >
> > > Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table")  
> 
> btw is it really a fix? From the description it's more like an
> optimization...
> 
I guess it depends on how the issue is perceived. There is no
functional problem but the flush is too coarse w/o this patch.

> > > Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> > > ---
> > >   drivers/iommu/intel/pasid.c | 11 ++++++++++-
> > >   1 file changed, 10 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/iommu/intel/pasid.c
> > > b/drivers/iommu/intel/pasid.c index c81f0f17c6ba..3991a24539a1
> > > 100644 --- a/drivers/iommu/intel/pasid.c
> > > +++ b/drivers/iommu/intel/pasid.c
> > > @@ -486,7 +486,16 @@ devtlb_invalidation_with_pasid(struct  
> > intel_iommu *iommu,  
> > >   	qdep = info->ats_qdep;
> > >   	pfsid = info->pfsid;
> > >
> > > -	qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 -
> > > VTD_PAGE_SHIFT);
> > > +	/*
> > > +	 * When PASID 0 is used, it indicates RID2PASID(DMA
> > > request w/o  
> > PASID),  
> > > +	 * devTLB flush w/o PASID should be used. For non-zero
> > > PASID under
> > > +	 * SVA usage, device could do DMA with multiple PASIDs.
> > > It is more
> > > +	 * efficient to flush devTLB specific to the PASID.
> > > +	 */
> > > +	if (pasid)  
> > 
> > How about
> > 
> > 	if (pasid == PASID_RID2PASID)
> > 		qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 -
> > VTD_PAGE_SHIFT);
> > 	else
> > 		qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid,
> > qdep, 0, 64 -
> > VTD_PAGE_SHIFT);
> > 
> > ?
> > 
> > It makes the code more readable and still works even we reassign
> > another pasid for RID2PASID.
> > 
> > Best regards,
> > baolu
> >   
> > > +		qi_flush_dev_iotlb_pasid(iommu, sid, pfsid,
> > > pasid, qdep, 0,  
> > 64 - VTD_PAGE_SHIFT);  
> > > +	else
> > > +		qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0,
> > > 64 -  
> > VTD_PAGE_SHIFT);  
> > >   }
> > >
> > >   void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
> > > struct  
> > device *dev,  
> > >  

[Jacob Pan]
_______________________________________________
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iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

  reply	other threads:[~2020-06-30  4:52 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-23 15:43 [PATCH 0/7] iommu/vt-d: Misc tweaks and fixes for vSVA Jacob Pan
2020-06-23 15:43 ` [PATCH 1/7] iommu/vt-d: Enforce PASID devTLB field mask Jacob Pan
2020-06-25  7:14   ` Lu Baolu
2020-06-23 15:43 ` [PATCH 2/7] iommu/vt-d: Remove global page support in devTLB flush Jacob Pan
2020-06-25  7:17   ` Lu Baolu
2020-06-23 15:43 ` [PATCH 3/7] iommu/vt-d: Fix PASID devTLB invalidation Jacob Pan
2020-06-25  7:25   ` Lu Baolu
2020-06-30  3:01     ` Tian, Kevin
2020-06-30  4:58       ` Jacob Pan [this message]
2020-06-30  4:57     ` Jacob Pan
2020-06-23 15:43 ` [PATCH 4/7] iommu/vt-d: Handle non-page aligned address Jacob Pan
2020-06-25 10:05   ` Lu Baolu
2020-06-30 17:19     ` Jacob Pan
2020-06-23 15:43 ` [PATCH 5/7] iommu/vt-d: Fix devTLB flush for vSVA Jacob Pan
2020-06-23 20:12   ` kernel test robot
2020-06-24  0:38   ` Jacob Pan
2020-06-23 15:43 ` [PATCH 6/7] iommu/vt-d: Warn on out-of-range invalidation address Jacob Pan
2020-06-25 10:10   ` Lu Baolu
2020-06-30 17:34     ` Jacob Pan
2020-07-01  1:45       ` Lu Baolu
2020-07-01 14:19         ` Jacob Pan
2020-06-23 15:43 ` [PATCH 7/7] iommu/vt-d: Disable multiple GPASID-dev bind Jacob Pan
2020-06-25 12:54   ` Lu Baolu

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