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[216.228.112.21]) by smtp.gmail.com with ESMTPSA id z1sm458786pjz.10.2020.06.29.15.39.06 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Jun 2020 15:39:07 -0700 (PDT) Date: Mon, 29 Jun 2020 15:38:34 -0700 From: Nicolin Chen To: Krishna Reddy Subject: Re: [PATCH v7 3/3] iommu/arm-smmu: Add global/context fault implementation hooks Message-ID: <20200629223833.GE27967@Asurada-Nvidia> References: <20200629022838.29628-1-vdumpa@nvidia.com> <20200629022838.29628-4-vdumpa@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200629022838.29628-4-vdumpa@nvidia.com> User-Agent: Mutt/1.9.4 (2018-02-28) Cc: snikam@nvidia.com, mperttunen@nvidia.com, bhuntsman@nvidia.com, will@kernel.org, linux-kernel@vger.kernel.org, praithatha@nvidia.com, talho@nvidia.com, iommu@lists.linux-foundation.org, nicolinc@nvidia.com, linux-tegra@vger.kernel.org, yhsu@nvidia.com, treding@nvidia.com, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, bbiswas@nvidia.com X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Sun, Jun 28, 2020 at 07:28:38PM -0700, Krishna Reddy wrote: > Add global/context fault hooks to allow NVIDIA SMMU implementation > handle faults across multiple SMMUs. > > Signed-off-by: Krishna Reddy > +static irqreturn_t nvidia_smmu_global_fault_inst(int irq, > + struct arm_smmu_device *smmu, > + int inst) > +{ > + u32 gfsr, gfsynr0, gfsynr1, gfsynr2; > + void __iomem *gr0_base = nvidia_smmu_page(smmu, inst, 0); > + > + gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); > + gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); > + gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); > + gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); > + > + if (!gfsr) > + return IRQ_NONE; Could move this before gfsynr readings to save some readl() for !gfsr cases? > +static irqreturn_t nvidia_smmu_context_fault_bank(int irq, > + void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx); [...] > + fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); [...] > + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR); It reads FSR of the default inst (1st), but clears the FSR of corresponding inst -- just want to make sure that this is okay and intended. > @@ -185,7 +283,8 @@ struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu) > } > > nvidia_smmu->smmu.impl = &nvidia_smmu_impl; > - /* Free the arm_smmu_device struct allocated in arm-smmu.c. > + /* > + * Free the arm_smmu_device struct allocated in arm-smmu.c. > * Once this function returns, arm-smmu.c would use arm_smmu_device > * allocated as part of nvidia_smmu struct. > */ Hmm, this coding style fix should be probably squashed into PATCH-1? _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu