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From: Jacob Pan <jacob.jun.pan@linux.intel.com>
To: Lu Baolu <baolu.lu@linux.intel.com>
Cc: "Tian, Kevin" <kevin.tian@intel.com>,
	Raj Ashok <ashok.raj@intel.com>,
	LKML <linux-kernel@vger.kernel.org>,
	iommu@lists.linux-foundation.org,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH v2 3/7] iommu/vt-d: Fix PASID devTLB invalidation
Date: Wed, 1 Jul 2020 07:20:19 -0700	[thread overview]
Message-ID: <20200701072019.2afd1cc1@jacob-builder> (raw)
In-Reply-To: <6f970f1f-621e-f66e-79d4-f2871c121baa@linux.intel.com>

On Wed, 1 Jul 2020 08:49:54 +0800
Lu Baolu <baolu.lu@linux.intel.com> wrote:

> Hi Jacob,
> 
> On 7/1/20 5:07 AM, Jacob Pan wrote:
> > DevTLB flush can be used for both DMA request with and without
> > PASIDs. The former uses PASID#0 (RID2PASID), latter uses non-zero
> > PASID for SVA usage.
> > 
> > This patch adds a check for PASID value such that devTLB flush with
> > PASID is used for SVA case. This is more efficient in that multiple
> > PASIDs can be used by a single device, when tearing down a PASID
> > entry we shall flush only the devTLB specific to a PASID.
> > 
> > Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table")
> > Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> > ---
> >   drivers/iommu/intel/pasid.c | 11 ++++++++++-
> >   1 file changed, 10 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/iommu/intel/pasid.c
> > b/drivers/iommu/intel/pasid.c index c81f0f17c6ba..70d21209dd04
> > 100644 --- a/drivers/iommu/intel/pasid.c
> > +++ b/drivers/iommu/intel/pasid.c
> > @@ -486,7 +486,16 @@ devtlb_invalidation_with_pasid(struct
> > intel_iommu *iommu, qdep = info->ats_qdep;
> >   	pfsid = info->pfsid;
> >   
> > -	qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 -
> > VTD_PAGE_SHIFT);
> > +	/*
> > +	 * When PASID 0 is used, it indicates RID2PASID(DMA
> > request w/o PASID),
> > +	 * devTLB flush w/o PASID should be used. For non-zero
> > PASID under
> > +	 * SVA usage, device could do DMA with multiple PASIDs. It
> > is more
> > +	 * efficient to flush devTLB specific to the PASID.
> > +	 */
> > +	if (pasid == PASID_RID2PASID)
> > +		qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid,
> > qdep, 0, 64 - VTD_PAGE_SHIFT);
> > +	else
> > +		qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64
> > - VTD_PAGE_SHIFT);  
> 
> The if/else logic is reversed.
> 
> 	if (pasid == PASID_RID2PASID)
> 		qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 -
> VTD_PAGE_SHIFT); else
> 		qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid,
> qdep, 0, 64 - VTD_PAGE_SHIFT);
> 
indeed, will fix. thanks

> Best regards,
> baolu
> 
> >   }
> >   
> >   void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
> > struct device *dev, 

[Jacob Pan]
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  reply	other threads:[~2020-07-01 14:13 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-30 21:07 [PATCH v2 0/7] iommu/vt-d: Misc tweaks and fixes for vSVA Jacob Pan
2020-06-30 21:07 ` [PATCH v2 1/7] iommu/vt-d: Enforce PASID devTLB field mask Jacob Pan
2020-06-30 21:07 ` [PATCH v2 2/7] iommu/vt-d: Remove global page support in devTLB flush Jacob Pan
2020-06-30 21:07 ` [PATCH v2 3/7] iommu/vt-d: Fix PASID devTLB invalidation Jacob Pan
2020-07-01  0:49   ` Lu Baolu
2020-07-01 14:20     ` Jacob Pan [this message]
2020-06-30 21:07 ` [PATCH v2 4/7] iommu/vt-d: Handle non-page aligned address Jacob Pan
2020-07-01  1:08   ` Lu Baolu
2020-06-30 21:07 ` [PATCH v2 5/7] iommu/vt-d: Fix devTLB flush for vSVA Jacob Pan
2020-07-01  1:11   ` Lu Baolu
2020-06-30 21:07 ` [PATCH v2 6/7] iommu/vt-d: Warn on out-of-range invalidation address Jacob Pan
2020-06-30 21:07 ` [PATCH v2 7/7] iommu/vt-d: Disable multiple GPASID-dev bind Jacob Pan

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