From: Will Deacon <will@kernel.org>
To: Jean-Philippe Brucker <jean-philippe@linaro.org>
Cc: fenghua.yu@intel.com, Suzuki K Poulose <suzuki.poulose@arm.com>,
catalin.marinas@arm.com, zhengxiang9@huawei.com,
hch@infradead.org, linux-mm@kvack.org,
iommu@lists.linux-foundation.org, zhangfei.gao@linaro.org,
robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v8 07/12] iommu/arm-smmu-v3: Share process page tables
Date: Mon, 13 Jul 2020 21:22:37 +0100 [thread overview]
Message-ID: <20200713202236.GA3575@willie-the-truck> (raw)
In-Reply-To: <20200618155125.1548969-8-jean-philippe@linaro.org>
On Thu, Jun 18, 2020 at 05:51:20PM +0200, Jean-Philippe Brucker wrote:
> With Shared Virtual Addressing (SVA), we need to mirror CPU TTBR, TCR,
> MAIR and ASIDs in SMMU contexts. Each SMMU has a single ASID space split
> into two sets, shared and private. Shared ASIDs correspond to those
> obtained from the arch ASID allocator, and private ASIDs are used for
> "classic" map/unmap DMA.
>
> A possible conflict happens when trying to use a shared ASID that has
> already been allocated for private use by the SMMU driver. This will be
> addressed in a later patch by replacing the private ASID. At the
> moment we return -EBUSY.
>
> Each mm_struct shared with the SMMU will have a single context
> descriptor. Add a refcount to keep track of this. It will be protected
> by the global SVA lock.
>
> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> ---
> drivers/iommu/arm-smmu-v3.c | 150 +++++++++++++++++++++++++++++++++++-
> 1 file changed, 146 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index 937aa1af428d5..cabd942e4cbf3 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -22,6 +22,7 @@
> #include <linux/iommu.h>
> #include <linux/iopoll.h>
> #include <linux/module.h>
> +#include <linux/mmu_context.h>
> #include <linux/msi.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> @@ -33,6 +34,8 @@
>
> #include <linux/amba/bus.h>
>
> +#include "io-pgtable-arm.h"
> +
> /* MMIO registers */
> #define ARM_SMMU_IDR0 0x0
> #define IDR0_ST_LVL GENMASK(28, 27)
> @@ -589,6 +592,9 @@ struct arm_smmu_ctx_desc {
> u64 ttbr;
> u64 tcr;
> u64 mair;
> +
> + refcount_t refs;
> + struct mm_struct *mm;
> };
>
> struct arm_smmu_l1_ctx_desc {
> @@ -727,6 +733,7 @@ struct arm_smmu_option_prop {
> };
>
> static DEFINE_XARRAY_ALLOC1(asid_xa);
> +static DEFINE_MUTEX(sva_lock);
>
> static struct arm_smmu_option_prop arm_smmu_options[] = {
> { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
> @@ -1662,7 +1669,8 @@ static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain,
> #ifdef __BIG_ENDIAN
> CTXDESC_CD_0_ENDI |
> #endif
> - CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET |
> + CTXDESC_CD_0_R | CTXDESC_CD_0_A |
> + (cd->mm ? 0 : CTXDESC_CD_0_ASET) |
> CTXDESC_CD_0_AA64 |
> FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) |
> CTXDESC_CD_0_V;
> @@ -1766,12 +1774,144 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain)
> cdcfg->cdtab = NULL;
> }
>
> -static void arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd)
> +static void arm_smmu_init_cd(struct arm_smmu_ctx_desc *cd)
> {
> + refcount_set(&cd->refs, 1);
> +}
> +
> +static bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd)
> +{
> + bool free;
> + struct arm_smmu_ctx_desc *old_cd;
> +
> if (!cd->asid)
> - return;
> + return false;
> +
> + free = refcount_dec_and_test(&cd->refs);
> + if (free) {
> + old_cd = xa_erase(&asid_xa, cd->asid);
> + WARN_ON(old_cd != cd);
> + }
> + return free;
> +}
> +
> +static struct arm_smmu_ctx_desc *arm_smmu_share_asid(u16 asid)
> +{
> + struct arm_smmu_ctx_desc *cd;
>
> - xa_erase(&asid_xa, cd->asid);
> + cd = xa_load(&asid_xa, asid);
> + if (!cd)
> + return NULL;
> +
> + if (cd->mm) {
> + /* All devices bound to this mm use the same cd struct. */
> + refcount_inc(&cd->refs);
> + return cd;
> + }
How do you handle racing against a concurrent arm_smmu_free_asid() here?
> +__maybe_unused
> +static struct arm_smmu_ctx_desc *arm_smmu_alloc_shared_cd(struct mm_struct *mm)
> +{
> + u16 asid;
> + int ret = 0;
> + u64 tcr, par, reg;
> + struct arm_smmu_ctx_desc *cd;
> + struct arm_smmu_ctx_desc *old_cd = NULL;
> +
> + lockdep_assert_held(&sva_lock);
Please don't bother with these for static functions (but I can see the
value in having them for functions with external callers).
> +
> + asid = mm_context_get(mm);
> + if (!asid)
> + return ERR_PTR(-ESRCH);
> +
> + cd = kzalloc(sizeof(*cd), GFP_KERNEL);
> + if (!cd) {
> + ret = -ENOMEM;
> + goto err_put_context;
> + }
> +
> + arm_smmu_init_cd(cd);
> +
> + old_cd = arm_smmu_share_asid(asid);
> + if (IS_ERR(old_cd)) {
> + ret = PTR_ERR(old_cd);
> + goto err_free_cd;
> + } else if (old_cd) {
Don't need the 'else'
> + if (WARN_ON(old_cd->mm != mm)) {
> + ret = -EINVAL;
> + goto err_free_cd;
> + }
> + kfree(cd);
> + mm_context_put(mm);
> + return old_cd;
This is a bit messy. Can you consolidate the return path so that ret is a
pointer and you have an 'int err', e.g.:
return err < 0 ? ERR_PTR(err) : ret;
Will
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next prev parent reply other threads:[~2020-07-13 20:22 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-18 15:51 [PATCH v8 00/12] iommu: Shared Virtual Addressing for SMMUv3 (PT sharing part) Jean-Philippe Brucker
2020-06-18 15:51 ` [PATCH v8 01/12] mm: Define pasid in mm Jean-Philippe Brucker
2020-06-18 15:51 ` [PATCH v8 02/12] iommu/ioasid: Add ioasid references Jean-Philippe Brucker
2020-06-18 15:51 ` [PATCH v8 03/12] iommu/sva: Add PASID helpers Jean-Philippe Brucker
2020-06-19 7:37 ` Lu Baolu
2020-06-18 15:51 ` [PATCH v8 04/12] arm64: mm: Pin down ASIDs for sharing mm with devices Jean-Philippe Brucker
2020-07-13 15:46 ` Will Deacon
2020-07-16 15:44 ` Jean-Philippe Brucker
2020-06-18 15:51 ` [PATCH v8 05/12] iommu/io-pgtable-arm: Move some definitions to a header Jean-Philippe Brucker
2020-06-18 15:51 ` [PATCH v8 06/12] arm64: cpufeature: Export symbol read_sanitised_ftr_reg() Jean-Philippe Brucker
2020-06-18 15:51 ` [PATCH v8 07/12] iommu/arm-smmu-v3: Share process page tables Jean-Philippe Brucker
2020-07-13 20:22 ` Will Deacon [this message]
2020-07-16 15:45 ` Jean-Philippe Brucker
2020-06-18 15:51 ` [PATCH v8 08/12] iommu/arm-smmu-v3: Seize private ASID Jean-Philippe Brucker
2020-07-06 12:40 ` Xiang Zheng
2020-07-06 16:07 ` Jean-Philippe Brucker
2020-06-18 15:51 ` [PATCH v8 09/12] iommu/arm-smmu-v3: Check for SVA features Jean-Philippe Brucker
2020-06-18 15:51 ` [PATCH v8 10/12] iommu/arm-smmu-v3: Add SVA device feature Jean-Philippe Brucker
2020-06-18 15:51 ` [PATCH v8 11/12] iommu/arm-smmu-v3: Implement iommu_sva_bind/unbind() Jean-Philippe Brucker
2020-06-18 15:51 ` [PATCH v8 12/12] iommu/arm-smmu-v3: Hook up ATC invalidation to mm ops Jean-Philippe Brucker
2020-07-09 9:39 ` [PATCH v8 00/12] iommu: Shared Virtual Addressing for SMMUv3 (PT sharing part) Jean-Philippe Brucker
2020-07-20 11:11 ` Will Deacon
2020-07-20 15:39 ` Jean-Philippe Brucker
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