From: Joerg Roedel <joro@8bytes.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org, jonathan.lemon@gmail.com,
dwmw2@infradead.org, hch@lst.de,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/2] iommu/dma: Avoid SAC address trick for PCIe devices
Date: Wed, 22 Jul 2020 14:48:55 +0200 [thread overview]
Message-ID: <20200722124854.GZ27672@8bytes.org> (raw)
In-Reply-To: <ad3f66c8-7772-731d-cd0a-c5d6d46297cb@arm.com>
On Tue, Jul 14, 2020 at 12:42:36PM +0100, Robin Murphy wrote:
> Oh bother - yes, this could have been masking all manner of bugs. That
> system will presumably also break if you managed to exhaust the 32-bit IOVA
> space such that the allocator moved up to the higher range anyway, or if you
> passed the XHCI through to a VM with a sufficiently wacky GPA layout, but I
> guess those are cases that simply nobody's run into yet.
>
> Does the firmware actually report any upper address constraint such that
> Sebastian's IVRS aperture patches might help?
No, it doesn't. I am not sure what the best way is to get these issues
found and fixed. I doubt they will be getting fixed when the allocation
pattern isn't changed, maybe we can put your changes behind a config
variable and start testing/reporting bugs/etc.
Regards,
Joerg
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next prev parent reply other threads:[~2020-07-22 12:49 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-08 11:32 [PATCH 1/2] iommu/intel: Avoid SAC address trick for PCIe devices Robin Murphy
2020-07-08 11:32 ` [PATCH 2/2] iommu/dma: " Robin Murphy
2020-07-13 13:14 ` Joerg Roedel
2020-07-14 11:42 ` Robin Murphy
2020-07-22 12:48 ` Joerg Roedel [this message]
2020-07-08 12:26 ` [PATCH 1/2] iommu/intel: " Christoph Hellwig
2020-07-10 14:20 ` Joerg Roedel
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