iommu.lists.linux-foundation.org archive mirror
 help / color / mirror / Atom feed
From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Dimitri Sivanich <sivanich@hpe.com>,
	linux-hyperv@vger.kernel.org, Steve Wahl <steve.wahl@hpe.com>,
	linux-pci@vger.kernel.org, "K. Y. Srinivasan" <kys@microsoft.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Wei Liu <wei.liu@kernel.org>,
	Stephen Hemminger <sthemmin@microsoft.com>,
	Baolu Lu <baolu.lu@intel.com>, Marc Zyngier <maz@kernel.org>,
	x86@kernel.org, Jason Gunthorpe <jgg@mellanox.com>,
	Megha Dey <megha.dey@intel.com>,
	xen-devel@lists.xenproject.org, Kevin Tian <kevin.tian@intel.com>,
	Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	Haiyang Zhang <haiyangz@microsoft.com>,
	Alex Williamson <alex.williamson@redhat.com>,
	Stefano Stabellini <sstabellini@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Boris Ostrovsky <boris.ostrovsky@oracle.com>,
	Jon Derrick <jonathan.derrick@intel.com>,
	Juergen Gross <jgross@suse.com>, Russ Anderson <rja@hpe.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	iommu@lists.linux-foundation.org,
	Jacob Pan <jacob.jun.pan@intel.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>
Subject: [patch V2 42/46] genirq/proc: Take buslock on affinity write
Date: Wed, 26 Aug 2020 13:17:10 +0200	[thread overview]
Message-ID: <20200826112334.795343913@linutronix.de> (raw)
In-Reply-To: 20200826111628.794979401@linutronix.de

Until now interrupt chips which support setting affinity are nit locking
the associated bus lock for two reasons:

 - All chips which support affinity setting do not use buslock because they just
   can operated directly on the hardware.

 - All chips which use buslock do not support affinity setting because
   their interrupt chips are not capable. These chips are usually connected
   over a bus like I2C, SPI etc. and have an interrupt output which is
   conneted to CPU interrupt of some sort. So there is no way to set the
   affinity on the chip itself.

Upcoming hardware which is PCIE based sports a non standard MSI(X) variant
which stores the MSI message in RAM which is associated to e.g. a device
queue. The device manages this RAM and writes have to be issued via command
queues or similar mechanisms which is obviously not possible from interrupt
disabled, raw spinlock held context.

The buslock mechanism of irq chips can be utilized to support that. The
affinity write to the chip writes to shadow state, marks it pending and the
irq chip's irq_bus_sync_unlock() callback handles the command queue and
wait for completion similar to the other chip operations on I2C or SPI
busses.

Change the locking in irq_set_affinity() to bus_lock/unlock to help with
that. There are a few other callers than the proc interface, but none of
them is affected by this change as none of them affects an irq chip with
bus lock support.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
V2: New patch
---
 kernel/irq/manage.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
--- a/kernel/irq/manage.c
+++ b/kernel/irq/manage.c
@@ -373,16 +373,16 @@ int irq_set_affinity_locked(struct irq_d
 
 int __irq_set_affinity(unsigned int irq, const struct cpumask *mask, bool force)
 {
-	struct irq_desc *desc = irq_to_desc(irq);
+	struct irq_desc *desc;
 	unsigned long flags;
 	int ret;
 
+	desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
 	if (!desc)
 		return -EINVAL;
 
-	raw_spin_lock_irqsave(&desc->lock, flags);
 	ret = irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask, force);
-	raw_spin_unlock_irqrestore(&desc->lock, flags);
+	irq_put_desc_busunlock(desc, flags);
 	return ret;
 }
 

_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

  parent reply	other threads:[~2020-08-26 12:08 UTC|newest]

Thread overview: 121+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-26 11:16 [patch V2 00/46] x86, PCI, XEN, genirq ...: Prepare for device MSI Thomas Gleixner
2020-08-26 11:16 ` [patch V2 01/46] iommu/amd: Prevent NULL pointer dereference Thomas Gleixner
2020-08-27 14:57   ` Joerg Roedel
2020-08-26 11:16 ` [patch V2 02/46] x86/init: Remove unused init ops Thomas Gleixner
2020-08-26 11:16 ` [patch V2 03/46] PCI: vmd: Dont abuse vector irqomain as parent Thomas Gleixner
2020-08-26 11:16 ` [patch V2 04/46] genirq/chip: Use the first chip in irq_chip_compose_msi_msg() Thomas Gleixner
2020-08-26 19:50   ` Marc Zyngier
2020-08-26 21:19     ` Thomas Gleixner
2020-08-26 21:32       ` Marc Zyngier
2020-08-26 11:16 ` [patch V2 05/46] x86/msi: Move compose message callback where it belongs Thomas Gleixner
2020-08-26 11:16 ` [patch V2 06/46] x86/msi: Remove pointless vcpu_affinity callback Thomas Gleixner
2020-08-26 11:16 ` [patch V2 07/46] x86/irq: Rename X86_IRQ_ALLOC_TYPE_MSI* to reflect PCI dependency Thomas Gleixner
2020-08-26 11:16 ` [patch V2 08/46] x86/irq: Add allocation type for parent domain retrieval Thomas Gleixner
2020-08-26 11:16 ` [patch V2 09/46] iommu/vt-d: Consolidate irq domain getter Thomas Gleixner
2020-08-26 11:16 ` [patch V2 10/46] iommu/amd: " Thomas Gleixner
2020-08-26 11:16 ` [patch V2 11/46] iommu/irq_remapping: Consolidate irq domain lookup Thomas Gleixner
2020-08-26 11:16 ` [patch V2 12/46] x86/irq: Prepare consolidation of irq_alloc_info Thomas Gleixner
2020-08-26 11:16 ` [patch V2 13/46] x86/msi: Consolidate HPET allocation Thomas Gleixner
2020-08-26 11:16 ` [patch V2 14/46] x86/ioapic: Consolidate IOAPIC allocation Thomas Gleixner
2020-09-08 13:35   ` Wei Liu
2020-08-26 11:16 ` [patch V2 15/46] x86/irq: Consolidate DMAR irq allocation Thomas Gleixner
2020-08-26 16:50   ` Dey, Megha
2020-08-26 18:32     ` Thomas Gleixner
2020-08-26 20:50       ` Thomas Gleixner
2020-08-28  0:12         ` Dey, Megha
2020-08-26 11:16 ` [patch V2 16/46] x86/irq: Consolidate UV domain allocation Thomas Gleixner
2020-08-26 11:16 ` [patch V2 17/46] PCI/MSI: Rework pci_msi_domain_calc_hwirq() Thomas Gleixner
2020-08-26 20:24   ` Marc Zyngier
2020-08-26 11:16 ` [patch V2 18/46] x86/msi: Consolidate MSI allocation Thomas Gleixner
2020-09-08 13:36   ` Wei Liu
2020-08-26 11:16 ` [patch V2 19/46] x86/msi: Use generic MSI domain ops Thomas Gleixner
2020-08-26 20:21   ` Marc Zyngier
2020-08-26 20:43     ` Thomas Gleixner
2020-08-26 11:16 ` [patch V2 20/46] x86/irq: Move apic_post_init() invocation to one place Thomas Gleixner
2020-08-26 11:16 ` [patch V2 21/46] x86/pci: Reducde #ifdeffery in PCI init code Thomas Gleixner
2020-08-26 11:16 ` [patch V2 22/46] x86/irq: Initialize PCI/MSI domain at PCI init time Thomas Gleixner
2020-08-26 11:16 ` [patch V2 23/46] irqdomain/msi: Provide DOMAIN_BUS_VMD_MSI Thomas Gleixner
2020-08-26 20:42   ` Marc Zyngier
2020-08-26 20:57     ` Derrick, Jonathan
2020-08-26 11:16 ` [patch V2 24/46] PCI: vmd: Mark VMD irqdomain with DOMAIN_BUS_VMD_MSI Thomas Gleixner
2020-08-26 20:47   ` Marc Zyngier
2020-08-31 14:39   ` Jason Gunthorpe
2020-09-30 12:45     ` Derrick, Jonathan
2020-09-30 12:57       ` Jason Gunthorpe
2020-09-30 13:08         ` Derrick, Jonathan
2020-09-30 18:47           ` Jason Gunthorpe
2020-08-26 11:16 ` [patch V2 25/46] PCI/MSI: Provide pci_dev_has_special_msi_domain() helper Thomas Gleixner
2020-08-26 11:16 ` [patch V2 26/46] x86/xen: Make xen_msi_init() static and rename it to xen_hvm_msi_init() Thomas Gleixner
2020-08-26 11:16 ` [patch V2 27/46] x86/xen: Rework MSI teardown Thomas Gleixner
2020-08-27  7:46   ` Jürgen Groß
2020-08-26 11:16 ` [patch V2 28/46] x86/xen: Consolidate XEN-MSI init Thomas Gleixner
2020-08-27  7:47   ` Jürgen Groß
2020-08-26 11:16 ` [patch V2 29/46] irqdomain/msi: Allow to override msi_domain_alloc/free_irqs() Thomas Gleixner
2020-08-26 19:06   ` Marc Zyngier
2020-08-26 19:47     ` Thomas Gleixner
2020-08-26 21:33       ` Marc Zyngier
2020-08-28  0:24   ` Dey, Megha
2020-08-26 11:16 ` [patch V2 30/46] x86/xen: Wrap XEN MSI management into irqdomain Thomas Gleixner
2020-08-26 11:16 ` [patch V2 31/46] iommm/vt-d: Store irq domain in struct device Thomas Gleixner
2020-08-26 11:17 ` [patch V2 32/46] iommm/amd: " Thomas Gleixner
2020-08-26 11:17 ` [patch V2 33/46] x86/pci: Set default irq domain in pcibios_add_device() Thomas Gleixner
2020-08-26 11:17 ` [patch V2 34/46] PCI/MSI: Make arch_.*_msi_irq[s] fallbacks selectable Thomas Gleixner
2020-08-26 15:53   ` Thomas Gleixner
2020-08-26 21:14   ` Marc Zyngier
2020-08-26 21:27     ` Thomas Gleixner
2020-08-27 18:20   ` Bjorn Helgaas
2020-08-28 11:21     ` Lorenzo Pieralisi
2020-08-28 12:19       ` Jason Gunthorpe
2020-08-28 12:47         ` Marc Zyngier
2020-08-28 12:54           ` Jason Gunthorpe
2020-08-28 13:52             ` Marc Zyngier
2020-08-28 18:29     ` Thomas Gleixner
2020-09-25 13:54   ` Qian Cai
2020-09-26 12:38     ` Vasily Gorbik
2020-09-28 10:11       ` Thomas Gleixner
2020-08-26 11:17 ` [patch V2 35/46] x86/irq: Cleanup the arch_*_msi_irqs() leftovers Thomas Gleixner
2020-08-26 11:17 ` [patch V2 36/46] x86/irq: Make most MSI ops XEN private Thomas Gleixner
2020-08-26 11:17 ` [patch V2 37/46] iommu/vt-d: Remove domain search for PCI/MSI[X] Thomas Gleixner
2020-08-26 11:17 ` [patch V2 38/46] iommu/amd: Remove domain search for PCI/MSI Thomas Gleixner
2020-08-26 11:17 ` [patch V2 39/46] x86/irq: Add DEV_MSI allocation type Thomas Gleixner
2020-08-26 11:17 ` [patch V2 40/46] x86/msi: Rename and rework pci_msi_prepare() to cover non-PCI MSI Thomas Gleixner
2020-08-26 11:17 ` [patch V2 41/46] platform-msi: Provide default irq_chip:: Ack Thomas Gleixner
2020-08-26 21:25   ` Marc Zyngier
2020-08-26 11:17 ` Thomas Gleixner [this message]
2020-08-26 11:17 ` [patch V2 43/46] genirq/msi: Provide and use msi_domain_set_default_info_flags() Thomas Gleixner
2020-08-27  8:17   ` Marc Zyngier
2020-08-28 18:42     ` Thomas Gleixner
2020-08-26 11:17 ` [patch V2 44/46] platform-msi: Add device MSI infrastructure Thomas Gleixner
2020-08-26 11:17 ` [patch V2 45/46] irqdomain/msi: Provide msi_alloc/free_store() callbacks Thomas Gleixner
2020-08-26 11:17 ` [patch V2 46/46] irqchip: Add IMS (Interrupt Message Storm) driver - NOT FOR MERGING Thomas Gleixner
2020-08-31 14:45   ` Jason Gunthorpe
2020-08-28 11:41 ` [patch V2 00/46] x86, PCI, XEN, genirq ...: Prepare for device MSI Joerg Roedel
2020-08-31  0:51 ` Lu Baolu
2020-08-31  7:10   ` Thomas Gleixner
2020-08-31  7:29     ` Lu Baolu
2020-09-01  9:06 ` Boqun Feng
2020-09-03 16:35 ` Raj, Ashok
2020-09-03 18:12   ` Thomas Gleixner
2020-09-08  3:39 ` Russ Anderson
2020-09-25 15:29 ` Qian Cai
2020-09-25 15:49   ` Peter Zijlstra
2020-09-25 23:14     ` Thomas Gleixner
2020-09-27  8:46       ` [PATCH] x86/apic/msi: Unbreak DMAR and HPET MSI Thomas Gleixner
2020-09-29 23:03 ` [patch V2 00/46] x86, PCI, XEN, genirq ...: Prepare for device MSI Dey, Megha
2020-09-30  6:41   ` Thomas Gleixner
2020-09-30 11:43     ` Jason Gunthorpe
2020-09-30 15:20       ` Thomas Gleixner
2020-09-30 17:25         ` Dey, Megha
2020-09-30 18:11           ` Thomas Gleixner
2020-11-12 12:55 ` REGRESSION: " Jason Gunthorpe
2020-11-12 14:15   ` Thomas Gleixner
2020-11-12 15:18     ` Thomas Gleixner
2020-11-12 19:15       ` iommu/vt-d: Cure VF irqdomain hickup Thomas Gleixner
2020-11-12 21:34         ` Thomas Gleixner
2020-11-13  9:19           ` Marc Zyngier
2020-11-13 13:52             ` Thomas Gleixner
2020-11-13  7:20         ` Lu Baolu
2020-11-16  9:47         ` Geert Uytterhoeven
2020-11-16 12:50           ` Thomas Gleixner
2020-11-16 12:50           ` Lu Baolu
2020-11-16 23:22         ` Jason Gunthorpe

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200826112334.795343913@linutronix.de \
    --to=tglx@linutronix.de \
    --cc=alex.williamson@redhat.com \
    --cc=baolu.lu@intel.com \
    --cc=bhelgaas@google.com \
    --cc=boris.ostrovsky@oracle.com \
    --cc=dan.j.williams@intel.com \
    --cc=dave.jiang@intel.com \
    --cc=gregkh@linuxfoundation.org \
    --cc=haiyangz@microsoft.com \
    --cc=iommu@lists.linux-foundation.org \
    --cc=jacob.jun.pan@intel.com \
    --cc=jgg@mellanox.com \
    --cc=jgross@suse.com \
    --cc=jonathan.derrick@intel.com \
    --cc=kevin.tian@intel.com \
    --cc=konrad.wilk@oracle.com \
    --cc=kys@microsoft.com \
    --cc=linux-hyperv@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=maz@kernel.org \
    --cc=megha.dey@intel.com \
    --cc=rafael@kernel.org \
    --cc=rja@hpe.com \
    --cc=sivanich@hpe.com \
    --cc=sstabellini@kernel.org \
    --cc=steve.wahl@hpe.com \
    --cc=sthemmin@microsoft.com \
    --cc=wei.liu@kernel.org \
    --cc=x86@kernel.org \
    --cc=xen-devel@lists.xenproject.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).