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Thu, 24 Sep 2020 03:13:58 -0700 (PDT) Date: Thu, 24 Sep 2020 12:13:40 +0200 From: Jean-Philippe Brucker To: Shameerali Kolothum Thodi Subject: Re: [PATCH v10 10/13] iommu/arm-smmu-v3: Check for SVA features Message-ID: <20200924101340.GC170808@myrica> References: <20200918101852.582559-1-jean-philippe@linaro.org> <20200918101852.582559-11-jean-philippe@linaro.org> <753bcd76c21c4ea98ef1d4e492db01f4@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <753bcd76c21c4ea98ef1d4e492db01f4@huawei.com> Cc: "fenghua.yu@intel.com" , "will@kernel.org" , Suzuki K Poulose , "catalin.marinas@arm.com" , "linux-mm@kvack.org" , "iommu@lists.linux-foundation.org" , "zhangfei.gao@linaro.org" , "robin.murphy@arm.com" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Shameer, On Mon, Sep 21, 2020 at 08:59:39AM +0000, Shameerali Kolothum Thodi wrote: > > +bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) > > +{ > > + unsigned long reg, fld; > > + unsigned long oas; > > + unsigned long asid_bits; > > + u32 feat_mask = ARM_SMMU_FEAT_BTM | > > ARM_SMMU_FEAT_COHERENCY; > > Why is BTM mandated for SVA? I couldn't find this requirement in SMMU spec > (Sorry if I missed it or this got discussed earlier). But if performance is the only concern here, > is it better just to allow it with a warning rather than limiting SMMUs without BTM? It's a performance concern and requires to support multiple configurations, but the spec allows it. Are there SMMUs without BTM that need it? Thanks, Jean _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu