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Thu, 24 Sep 2020 03:23:14 -0700 (PDT) Date: Thu, 24 Sep 2020 12:23:12 +0200 From: Thierry Reding To: Nicolin Chen Subject: Re: [PATCH 1/3] iommu/tegra-smmu: Do not use PAGE_SHIFT and PAGE_MASK Message-ID: <20200924102312.GG2483160@ulmo> References: <20200911071643.17212-1-nicoleotsuka@gmail.com> <20200911071643.17212-2-nicoleotsuka@gmail.com> MIME-Version: 1.0 In-Reply-To: <20200911071643.17212-2-nicoleotsuka@gmail.com> User-Agent: Mutt/1.14.7 (2020-08-29) Cc: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, jonathanh@nvidia.com, linux-tegra@vger.kernel.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============0526666954663973493==" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" --===============0526666954663973493== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="/i8j2F0k9BYX4qLc" Content-Disposition: inline --/i8j2F0k9BYX4qLc Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Sep 11, 2020 at 12:16:41AM -0700, Nicolin Chen wrote: > PAGE_SHIFT and PAGE_MASK are defined corresponding to the page size > for CPU virtual addresses, which means PAGE_SHIFT could be a number > other than 12, but tegra-smmu maintains fixed 4KB IOVA pages and has > fixed [21:12] bit range for PTE entries. >=20 > So this patch replaces all PAGE_SHIFT/PAGE_MASK references with the > macros defined with SMMU_PTE_SHIFT. >=20 > Signed-off-by: Nicolin Chen > --- > drivers/iommu/tegra-smmu.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c > index 046add7acb61..789d21c01b77 100644 > --- a/drivers/iommu/tegra-smmu.c > +++ b/drivers/iommu/tegra-smmu.c > @@ -130,6 +130,11 @@ static inline u32 smmu_readl(struct tegra_smmu *smmu= , unsigned long offset) > #define SMMU_PDE_SHIFT 22 > #define SMMU_PTE_SHIFT 12 > =20 > +#define SMMU_PAGE_MASK (~(SMMU_SIZE_PT-1)) > +#define SMMU_OFFSET_IN_PAGE(x) ((unsigned long)(x) & ~SMMU_PAGE_MASK) > +#define SMMU_PFN_PHYS(x) ((phys_addr_t)(x) << SMMU_PTE_SHIFT) > +#define SMMU_PHYS_PFN(x) ((unsigned long)((x) >> SMMU_PTE_SHIFT)) > + > #define SMMU_PD_READABLE (1 << 31) > #define SMMU_PD_WRITABLE (1 << 30) > #define SMMU_PD_NONSECURE (1 << 29) > @@ -644,7 +649,7 @@ static void tegra_smmu_set_pte(struct tegra_smmu_as *= as, unsigned long iova, > u32 *pte, dma_addr_t pte_dma, u32 val) > { > struct tegra_smmu *smmu =3D as->smmu; > - unsigned long offset =3D offset_in_page(pte); > + unsigned long offset =3D SMMU_OFFSET_IN_PAGE(pte); > =20 > *pte =3D val; > =20 > @@ -726,7 +731,7 @@ __tegra_smmu_map(struct iommu_domain *domain, unsigne= d long iova, > pte_attrs |=3D SMMU_PTE_WRITABLE; > =20 > tegra_smmu_set_pte(as, iova, pte, pte_dma, > - __phys_to_pfn(paddr) | pte_attrs); > + SMMU_PHYS_PFN(paddr) | pte_attrs); > =20 > return 0; > } > @@ -790,7 +795,7 @@ static phys_addr_t tegra_smmu_iova_to_phys(struct iom= mu_domain *domain, > =20 > pfn =3D *pte & as->smmu->pfn_mask; > =20 > - return PFN_PHYS(pfn); > + return SMMU_PFN_PHYS(pfn); > } > =20 > static struct tegra_smmu *tegra_smmu_find(struct device_node *np) > @@ -1108,7 +1113,8 @@ struct tegra_smmu *tegra_smmu_probe(struct device *= dev, > smmu->dev =3D dev; > smmu->mc =3D mc; > =20 > - smmu->pfn_mask =3D BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1; > + smmu->pfn_mask =3D > + BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1; checkpatch no longer warns about lines longer than 80 characters. The new limit is 100, so you can fit this all on one line. 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