* [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-10-02 10:58 ` Krzysztof Kozlowski
2020-10-02 11:07 ` Krzysztof Kozlowski
2020-09-30 7:06 ` [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI " Yong Wu
` (23 subsequent siblings)
24 siblings, 2 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Convert MediaTek IOMMU to DT schema.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
.../bindings/iommu/mediatek,iommu.txt | 103 ------------
.../bindings/iommu/mediatek,iommu.yaml | 154 ++++++++++++++++++
2 files changed, 154 insertions(+), 103 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
deleted file mode 100644
index c1ccd8582eb2..000000000000
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-* Mediatek IOMMU Architecture Implementation
-
- Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and
-this M4U have two generations of HW architecture. Generation one uses flat
-pagetable, and only supports 4K size page mapping. Generation two uses the
-ARM Short-Descriptor translation table format for address translation.
-
- About the M4U Hardware Block Diagram, please check below:
-
- EMI (External Memory Interface)
- |
- m4u (Multimedia Memory Management Unit)
- |
- +--------+
- | |
- gals0-rx gals1-rx (Global Async Local Sync rx)
- | |
- | |
- gals0-tx gals1-tx (Global Async Local Sync tx)
- | | Some SoCs may have GALS.
- +--------+
- |
- SMI Common(Smart Multimedia Interface Common)
- |
- +----------------+-------
- | |
- | gals-rx There may be GALS in some larbs.
- | |
- | |
- | gals-tx
- | |
- SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
- (display) (vdec)
- | |
- | |
- +-----+-----+ +----+----+
- | | | | | |
- | | |... | | | ... There are different ports in each larb.
- | | | | | |
-OVL0 RDMA0 WDMA0 MC PP VLD
-
- As above, The Multimedia HW will go through SMI and M4U while it
-access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
-smi local arbiter and smi common. It will control whether the Multimedia
-HW should go though the m4u for translation or bypass it and talk
-directly with EMI. And also SMI help control the power domain and clocks for
-each local arbiter.
- Normally we specify a local arbiter(larb) for each multimedia HW
-like display, video decode, and camera. And there are different ports
-in each larb. Take a example, There are many ports like MC, PP, VLD in the
-video decode local arbiter, all these ports are according to the video HW.
- In some SoCs, there may be a GALS(Global Async Local Sync) module between
-smi-common and m4u, and additional GALS module between smi-larb and
-smi-common. GALS can been seen as a "asynchronous fifo" which could help
-synchronize for the modules in different clock frequency.
-
-Required properties:
-- compatible : must be one of the following string:
- "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
- "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
- "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW.
- "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
- generation one m4u HW.
- "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
- "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
-- reg : m4u register base and size.
-- interrupts : the interrupt of m4u.
-- clocks : must contain one entry for each clock-names.
-- clock-names : Only 1 optional clock:
- - "bclk": the block clock of m4u.
- Here is the list which require this "bclk":
- - mt2701, mt2712, mt7623 and mt8173.
- Note that m4u use the EMI clock which always has been enabled before kernel
- if there is no this "bclk".
-- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
- Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
- according to the local arbiter index, like larb0, larb1, larb2...
-- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
- Specifies the mtk_m4u_id as defined in
- dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
- dt-binding/memory/mt2712-larb-port.h for mt2712,
- dt-binding/memory/mt6779-larb-port.h for mt6779,
- dt-binding/memory/mt8173-larb-port.h for mt8173, and
- dt-binding/memory/mt8183-larb-port.h for mt8183.
-
-Example:
- iommu: iommu@10205000 {
- compatible = "mediatek,mt8173-m4u";
- reg = <0 0x10205000 0 0x1000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_M4U>;
- clock-names = "bclk";
- mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>;
- #iommu-cells = <1>;
- };
-
-Example for a client device:
- display {
- compatible = "mediatek,mt8173-disp";
- iommus = <&iommu M4U_PORT_DISP_OVL0>,
- <&iommu M4U_PORT_DISP_RDMA0>;
- ...
- };
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
new file mode 100644
index 000000000000..eae773ad53a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek IOMMU Architecture Implementation
+
+maintainers:
+ - Yong Wu <yong.wu@mediatek.com>
+
+description: |+
+ Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
+ this M4U have two generations of HW architecture. Generation one uses flat
+ pagetable, and only supports 4K size page mapping. Generation two uses the
+ ARM Short-Descriptor translation table format for address translation.
+
+ About the M4U Hardware Block Diagram, please check below:
+
+ EMI (External Memory Interface)
+ |
+ m4u (Multimedia Memory Management Unit)
+ |
+ +--------+
+ | |
+ gals0-rx gals1-rx (Global Async Local Sync rx)
+ | |
+ | |
+ gals0-tx gals1-tx (Global Async Local Sync tx)
+ | | Some SoCs may have GALS.
+ +--------+
+ |
+ SMI Common(Smart Multimedia Interface Common)
+ |
+ +----------------+-------
+ | |
+ | gals-rx There may be GALS in some larbs.
+ | |
+ | |
+ | gals-tx
+ | |
+ SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
+ (display) (vdec)
+ | |
+ | |
+ +-----+-----+ +----+----+
+ | | | | | |
+ | | |... | | | ... There are different ports in each larb.
+ | | | | | |
+ OVL0 RDMA0 WDMA0 MC PP VLD
+
+ As above, The Multimedia HW will go through SMI and M4U while it
+ access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
+ smi local arbiter and smi common. It will control whether the Multimedia
+ HW should go though the m4u for translation or bypass it and talk
+ directly with EMI. And also SMI help control the power domain and clocks for
+ each local arbiter.
+
+ Normally we specify a local arbiter(larb) for each multimedia HW
+ like display, video decode, and camera. And there are different ports
+ in each larb. Take a example, There are many ports like MC, PP, VLD in the
+ video decode local arbiter, all these ports are according to the video HW.
+
+ In some SoCs, there may be a GALS(Global Async Local Sync) module between
+ smi-common and m4u, and additional GALS module between smi-larb and
+ smi-common. GALS can been seen as a "asynchronous fifo" which could help
+ synchronize for the modules in different clock frequency.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt2701-m4u # mt2701 generation one HW
+ - mediatek,mt2712-m4u # mt2712 generation two HW
+ - mediatek,mt6779-m4u # mt6779 generation two HW
+ - mediatek,mt8173-m4u # mt8173 generation two HW
+ - mediatek,mt8183-m4u # mt8183 generation two HW
+
+ - description: mt7623 generation one HW
+ items:
+ - const: mediatek,mt7623-m4u
+ - const: mediatek,mt2701-m4u
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: |
+ bclk is optional. here is the list which require this bclk:
+ mt2701, mt2712, mt7623 and mt8173.
+ M4U will use the EMI clock which always has been enabled before
+ kernel if there is no this bclk.
+ items:
+ - description: bclk is the block clock.
+
+ clock-names:
+ items:
+ - const: bclk
+
+ mediatek,larbs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ List of phandle to the local arbiters in the current Socs.
+ Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
+ according to the local arbiter index, like larb0, larb1, larb2...
+
+ '#iommu-cells':
+ const: 1
+ description: |
+ This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
+ defined in
+ dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
+ dt-binding/memory/mt2712-larb-port.h for mt2712,
+ dt-binding/memory/mt6779-larb-port.h for mt6779,
+ dt-binding/memory/mt8173-larb-port.h for mt8173,
+ dt-binding/memory/mt8183-larb-port.h for mt8183.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - mediatek,larbs
+ - '#iommu-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ iommu: iommu@10205000 {
+ compatible = "mediatek,mt8173-m4u";
+ reg = <0x10205000 0x1000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_M4U>;
+ clock-names = "bclk";
+ mediatek,larbs = <&larb0 &larb1 &larb2
+ &larb3 &larb4 &larb5>;
+ #iommu-cells = <1>;
+ };
+
+ - |
+ #include <dt-bindings/memory/mt8173-larb-port.h>
+
+ /* Example for a client device */
+ display {
+ compatible = "mediatek,mt8173-disp";
+ iommus = <&iommu M4U_PORT_DISP_OVL0>,
+ <&iommu M4U_PORT_DISP_RDMA0>;
+ };
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema
2020-09-30 7:06 ` [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Yong Wu
@ 2020-10-02 10:58 ` Krzysztof Kozlowski
2020-10-30 9:47 ` Yong Wu
2020-10-02 11:07 ` Krzysztof Kozlowski
1 sibling, 1 reply; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-02 10:58 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:24PM +0800, Yong Wu wrote:
> Convert MediaTek IOMMU to DT schema.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> .../bindings/iommu/mediatek,iommu.txt | 103 ------------
> .../bindings/iommu/mediatek,iommu.yaml | 154 ++++++++++++++++++
> 2 files changed, 154 insertions(+), 103 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> deleted file mode 100644
> index c1ccd8582eb2..000000000000
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> +++ /dev/null
> @@ -1,103 +0,0 @@
> -* Mediatek IOMMU Architecture Implementation
> -
> - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and
> -this M4U have two generations of HW architecture. Generation one uses flat
> -pagetable, and only supports 4K size page mapping. Generation two uses the
> -ARM Short-Descriptor translation table format for address translation.
> -
> - About the M4U Hardware Block Diagram, please check below:
> -
> - EMI (External Memory Interface)
> - |
> - m4u (Multimedia Memory Management Unit)
> - |
> - +--------+
> - | |
> - gals0-rx gals1-rx (Global Async Local Sync rx)
> - | |
> - | |
> - gals0-tx gals1-tx (Global Async Local Sync tx)
> - | | Some SoCs may have GALS.
> - +--------+
> - |
> - SMI Common(Smart Multimedia Interface Common)
> - |
> - +----------------+-------
> - | |
> - | gals-rx There may be GALS in some larbs.
> - | |
> - | |
> - | gals-tx
> - | |
> - SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
> - (display) (vdec)
> - | |
> - | |
> - +-----+-----+ +----+----+
> - | | | | | |
> - | | |... | | | ... There are different ports in each larb.
> - | | | | | |
> -OVL0 RDMA0 WDMA0 MC PP VLD
> -
> - As above, The Multimedia HW will go through SMI and M4U while it
> -access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
> -smi local arbiter and smi common. It will control whether the Multimedia
> -HW should go though the m4u for translation or bypass it and talk
> -directly with EMI. And also SMI help control the power domain and clocks for
> -each local arbiter.
> - Normally we specify a local arbiter(larb) for each multimedia HW
> -like display, video decode, and camera. And there are different ports
> -in each larb. Take a example, There are many ports like MC, PP, VLD in the
> -video decode local arbiter, all these ports are according to the video HW.
> - In some SoCs, there may be a GALS(Global Async Local Sync) module between
> -smi-common and m4u, and additional GALS module between smi-larb and
> -smi-common. GALS can been seen as a "asynchronous fifo" which could help
> -synchronize for the modules in different clock frequency.
> -
> -Required properties:
> -- compatible : must be one of the following string:
> - "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
> - "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
> - "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW.
> - "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
> - generation one m4u HW.
> - "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
> - "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
> -- reg : m4u register base and size.
> -- interrupts : the interrupt of m4u.
> -- clocks : must contain one entry for each clock-names.
> -- clock-names : Only 1 optional clock:
> - - "bclk": the block clock of m4u.
> - Here is the list which require this "bclk":
> - - mt2701, mt2712, mt7623 and mt8173.
> - Note that m4u use the EMI clock which always has been enabled before kernel
> - if there is no this "bclk".
> -- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
> - Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
> - according to the local arbiter index, like larb0, larb1, larb2...
> -- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
> - Specifies the mtk_m4u_id as defined in
> - dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
> - dt-binding/memory/mt2712-larb-port.h for mt2712,
> - dt-binding/memory/mt6779-larb-port.h for mt6779,
> - dt-binding/memory/mt8173-larb-port.h for mt8173, and
> - dt-binding/memory/mt8183-larb-port.h for mt8183.
> -
> -Example:
> - iommu: iommu@10205000 {
> - compatible = "mediatek,mt8173-m4u";
> - reg = <0 0x10205000 0 0x1000>;
> - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&infracfg CLK_INFRA_M4U>;
> - clock-names = "bclk";
> - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>;
> - #iommu-cells = <1>;
> - };
> -
> -Example for a client device:
> - display {
> - compatible = "mediatek,mt8173-disp";
> - iommus = <&iommu M4U_PORT_DISP_OVL0>,
> - <&iommu M4U_PORT_DISP_RDMA0>;
> - ...
> - };
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> new file mode 100644
> index 000000000000..eae773ad53a3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -0,0 +1,154 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
You relicense GPLv2 content so you need acks/signed-offs from every
author:
- Fabien Parent <fparent@baylibre.com>
- Chao Hao <chao.hao@mediatek.com>
- Matthias Brugger <matthias.bgg@gmail.com>
- Honghui Zhang <honghui.zhang@mediatek.com>
(assuming yours is implicit).
Please resend CC-ing all the people.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek IOMMU Architecture Implementation
> +
> +maintainers:
> + - Yong Wu <yong.wu@mediatek.com>
> +
> +description: |+
> + Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
> + this M4U have two generations of HW architecture. Generation one uses flat
> + pagetable, and only supports 4K size page mapping. Generation two uses the
> + ARM Short-Descriptor translation table format for address translation.
> +
> + About the M4U Hardware Block Diagram, please check below:
> +
> + EMI (External Memory Interface)
> + |
> + m4u (Multimedia Memory Management Unit)
> + |
> + +--------+
> + | |
> + gals0-rx gals1-rx (Global Async Local Sync rx)
> + | |
> + | |
> + gals0-tx gals1-tx (Global Async Local Sync tx)
> + | | Some SoCs may have GALS.
> + +--------+
> + |
> + SMI Common(Smart Multimedia Interface Common)
> + |
> + +----------------+-------
> + | |
> + | gals-rx There may be GALS in some larbs.
> + | |
> + | |
> + | gals-tx
> + | |
> + SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
> + (display) (vdec)
> + | |
> + | |
> + +-----+-----+ +----+----+
> + | | | | | |
> + | | |... | | | ... There are different ports in each larb.
> + | | | | | |
> + OVL0 RDMA0 WDMA0 MC PP VLD
> +
> + As above, The Multimedia HW will go through SMI and M4U while it
> + access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
> + smi local arbiter and smi common. It will control whether the Multimedia
> + HW should go though the m4u for translation or bypass it and talk
> + directly with EMI. And also SMI help control the power domain and clocks for
> + each local arbiter.
> +
> + Normally we specify a local arbiter(larb) for each multimedia HW
> + like display, video decode, and camera. And there are different ports
> + in each larb. Take a example, There are many ports like MC, PP, VLD in the
> + video decode local arbiter, all these ports are according to the video HW.
> +
> + In some SoCs, there may be a GALS(Global Async Local Sync) module between
> + smi-common and m4u, and additional GALS module between smi-larb and
> + smi-common. GALS can been seen as a "asynchronous fifo" which could help
> + synchronize for the modules in different clock frequency.
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - mediatek,mt2701-m4u # mt2701 generation one HW
> + - mediatek,mt2712-m4u # mt2712 generation two HW
> + - mediatek,mt6779-m4u # mt6779 generation two HW
> + - mediatek,mt8173-m4u # mt8173 generation two HW
> + - mediatek,mt8183-m4u # mt8183 generation two HW
> +
> + - description: mt7623 generation one HW
> + items:
> + - const: mediatek,mt7623-m4u
> + - const: mediatek,mt2701-m4u
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + description: |
> + bclk is optional. here is the list which require this bclk:
> + mt2701, mt2712, mt7623 and mt8173.
> + M4U will use the EMI clock which always has been enabled before
> + kernel if there is no this bclk.
> + items:
> + - description: bclk is the block clock.
> +
> + clock-names:
> + items:
> + - const: bclk
> +
> + mediatek,larbs:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + List of phandle to the local arbiters in the current Socs.
> + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
> + according to the local arbiter index, like larb0, larb1, larb2...
How many items?
Best regards,
Krzysztof
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema
2020-10-02 10:58 ` Krzysztof Kozlowski
@ 2020-10-30 9:47 ` Yong Wu
0 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-10-30 9:47 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
Tomasz Figa, Robin Murphy, Will Deacon, linux-kernel, Evan Green,
chao.hao, iommu, Rob Herring, linux-mediatek, Matthias Brugger,
anan.sun, ming-fan.chen, Greg Kroah-Hartman, kernel-team,
linux-arm-kernel
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On Fri, 2020-10-02 at 12:58 +0200, Krzysztof Kozlowski wrote:
> On Wed, Sep 30, 2020 at 03:06:24PM +0800, Yong Wu wrote:
> > Convert MediaTek IOMMU to DT schema.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> > .../bindings/iommu/mediatek,iommu.txt | 103 ------------
> > .../bindings/iommu/mediatek,iommu.yaml | 154 ++++++++++++++++++
> > 2 files changed, 154 insertions(+), 103 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> > create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> >
...
> > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > new file mode 100644
> > index 000000000000..eae773ad53a3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > @@ -0,0 +1,154 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>
> You relicense GPLv2 content so you need acks/signed-offs from every
> author:
>
> - Fabien Parent <fparent@baylibre.com>
> - Chao Hao <chao.hao@mediatek.com>
> - Matthias Brugger <matthias.bgg@gmail.com>
> - Honghui Zhang <honghui.zhang@mediatek.com>
> (assuming yours is implicit).
>
> Please resend CC-ing all the people.
Sorry, I really missed this mail.
I have sent v4 only for smi. the iommu part still need some time.
The license "GPL-2.0-only OR BSD-2-Clause" is requested when we run
check_patch. That means each converting YAML need all contributors'
ack/SoB?
I have added their CC in v4 smi binding except honghui whose address is
not avalable now. I will act for him.
>
>
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek IOMMU Architecture Implementation
> > +
[snip..]
> > + mediatek,larbs:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: |
> > + List of phandle to the local arbiters in the current Socs.
> > + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
> > + according to the local arbiter index, like larb0, larb1, larb2...
>
> How many items?
I will add maxitems property.
Thanks.
>
> Best regards,
> Krzysztof
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
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_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema
2020-09-30 7:06 ` [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Yong Wu
2020-10-02 10:58 ` Krzysztof Kozlowski
@ 2020-10-02 11:07 ` Krzysztof Kozlowski
2020-10-06 4:26 ` Yong Wu
1 sibling, 1 reply; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-02 11:07 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:24PM +0800, Yong Wu wrote:
> Convert MediaTek IOMMU to DT schema.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> .../bindings/iommu/mediatek,iommu.txt | 103 ------------
> .../bindings/iommu/mediatek,iommu.yaml | 154 ++++++++++++++++++
> 2 files changed, 154 insertions(+), 103 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> deleted file mode 100644
> index c1ccd8582eb2..000000000000
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> +++ /dev/null
> @@ -1,103 +0,0 @@
> -* Mediatek IOMMU Architecture Implementation
> -
> - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and
> -this M4U have two generations of HW architecture. Generation one uses flat
> -pagetable, and only supports 4K size page mapping. Generation two uses the
> -ARM Short-Descriptor translation table format for address translation.
> -
> - About the M4U Hardware Block Diagram, please check below:
> -
> - EMI (External Memory Interface)
> - |
> - m4u (Multimedia Memory Management Unit)
> - |
> - +--------+
> - | |
> - gals0-rx gals1-rx (Global Async Local Sync rx)
> - | |
> - | |
> - gals0-tx gals1-tx (Global Async Local Sync tx)
> - | | Some SoCs may have GALS.
> - +--------+
> - |
> - SMI Common(Smart Multimedia Interface Common)
> - |
> - +----------------+-------
> - | |
> - | gals-rx There may be GALS in some larbs.
> - | |
> - | |
> - | gals-tx
> - | |
> - SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
> - (display) (vdec)
> - | |
> - | |
> - +-----+-----+ +----+----+
> - | | | | | |
> - | | |... | | | ... There are different ports in each larb.
> - | | | | | |
> -OVL0 RDMA0 WDMA0 MC PP VLD
> -
> - As above, The Multimedia HW will go through SMI and M4U while it
> -access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
> -smi local arbiter and smi common. It will control whether the Multimedia
> -HW should go though the m4u for translation or bypass it and talk
> -directly with EMI. And also SMI help control the power domain and clocks for
> -each local arbiter.
> - Normally we specify a local arbiter(larb) for each multimedia HW
> -like display, video decode, and camera. And there are different ports
> -in each larb. Take a example, There are many ports like MC, PP, VLD in the
> -video decode local arbiter, all these ports are according to the video HW.
> - In some SoCs, there may be a GALS(Global Async Local Sync) module between
> -smi-common and m4u, and additional GALS module between smi-larb and
> -smi-common. GALS can been seen as a "asynchronous fifo" which could help
> -synchronize for the modules in different clock frequency.
> -
> -Required properties:
> -- compatible : must be one of the following string:
> - "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
> - "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
> - "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW.
> - "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
> - generation one m4u HW.
> - "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
> - "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
> -- reg : m4u register base and size.
> -- interrupts : the interrupt of m4u.
> -- clocks : must contain one entry for each clock-names.
> -- clock-names : Only 1 optional clock:
> - - "bclk": the block clock of m4u.
> - Here is the list which require this "bclk":
> - - mt2701, mt2712, mt7623 and mt8173.
> - Note that m4u use the EMI clock which always has been enabled before kernel
> - if there is no this "bclk".
> -- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
> - Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
> - according to the local arbiter index, like larb0, larb1, larb2...
> -- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
> - Specifies the mtk_m4u_id as defined in
> - dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
> - dt-binding/memory/mt2712-larb-port.h for mt2712,
> - dt-binding/memory/mt6779-larb-port.h for mt6779,
> - dt-binding/memory/mt8173-larb-port.h for mt8173, and
> - dt-binding/memory/mt8183-larb-port.h for mt8183.
> -
> -Example:
> - iommu: iommu@10205000 {
> - compatible = "mediatek,mt8173-m4u";
> - reg = <0 0x10205000 0 0x1000>;
> - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&infracfg CLK_INFRA_M4U>;
> - clock-names = "bclk";
> - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>;
> - #iommu-cells = <1>;
> - };
> -
> -Example for a client device:
> - display {
> - compatible = "mediatek,mt8173-disp";
> - iommus = <&iommu M4U_PORT_DISP_OVL0>,
> - <&iommu M4U_PORT_DISP_RDMA0>;
> - ...
> - };
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> new file mode 100644
> index 000000000000..eae773ad53a3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -0,0 +1,154 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek IOMMU Architecture Implementation
> +
> +maintainers:
> + - Yong Wu <yong.wu@mediatek.com>
> +
> +description: |+
> + Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
> + this M4U have two generations of HW architecture. Generation one uses flat
> + pagetable, and only supports 4K size page mapping. Generation two uses the
> + ARM Short-Descriptor translation table format for address translation.
> +
> + About the M4U Hardware Block Diagram, please check below:
> +
> + EMI (External Memory Interface)
> + |
> + m4u (Multimedia Memory Management Unit)
> + |
> + +--------+
> + | |
> + gals0-rx gals1-rx (Global Async Local Sync rx)
> + | |
> + | |
> + gals0-tx gals1-tx (Global Async Local Sync tx)
> + | | Some SoCs may have GALS.
> + +--------+
> + |
> + SMI Common(Smart Multimedia Interface Common)
> + |
> + +----------------+-------
> + | |
> + | gals-rx There may be GALS in some larbs.
> + | |
> + | |
> + | gals-tx
> + | |
> + SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
> + (display) (vdec)
> + | |
> + | |
> + +-----+-----+ +----+----+
> + | | | | | |
> + | | |... | | | ... There are different ports in each larb.
> + | | | | | |
> + OVL0 RDMA0 WDMA0 MC PP VLD
> +
> + As above, The Multimedia HW will go through SMI and M4U while it
> + access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
> + smi local arbiter and smi common. It will control whether the Multimedia
> + HW should go though the m4u for translation or bypass it and talk
> + directly with EMI. And also SMI help control the power domain and clocks for
> + each local arbiter.
> +
> + Normally we specify a local arbiter(larb) for each multimedia HW
> + like display, video decode, and camera. And there are different ports
> + in each larb. Take a example, There are many ports like MC, PP, VLD in the
> + video decode local arbiter, all these ports are according to the video HW.
> +
> + In some SoCs, there may be a GALS(Global Async Local Sync) module between
> + smi-common and m4u, and additional GALS module between smi-larb and
> + smi-common. GALS can been seen as a "asynchronous fifo" which could help
> + synchronize for the modules in different clock frequency.
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - mediatek,mt2701-m4u # mt2701 generation one HW
> + - mediatek,mt2712-m4u # mt2712 generation two HW
> + - mediatek,mt6779-m4u # mt6779 generation two HW
> + - mediatek,mt8173-m4u # mt8173 generation two HW
> + - mediatek,mt8183-m4u # mt8183 generation two HW
> +
> + - description: mt7623 generation one HW
> + items:
> + - const: mediatek,mt7623-m4u
> + - const: mediatek,mt2701-m4u
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + description: |
> + bclk is optional. here is the list which require this bclk:
> + mt2701, mt2712, mt7623 and mt8173.
Similarly to my comment in other patch, this should be part of schema
within 'if-then'.
Best regards,
Krzysztof
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema
2020-10-02 11:07 ` Krzysztof Kozlowski
@ 2020-10-06 4:26 ` Yong Wu
2020-10-12 17:08 ` Krzysztof Kozlowski
0 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-10-06 4:26 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Fri, 2020-10-02 at 13:07 +0200, Krzysztof Kozlowski wrote:
> On Wed, Sep 30, 2020 at 03:06:24PM +0800, Yong Wu wrote:
> > Convert MediaTek IOMMU to DT schema.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> > .../bindings/iommu/mediatek,iommu.txt | 103 ------------
> > .../bindings/iommu/mediatek,iommu.yaml | 154 ++++++++++++++++++
> > 2 files changed, 154 insertions(+), 103 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> > create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> >
[...]
> > +properties:
> > + compatible:
> > + oneOf:
> > + - enum:
> > + - mediatek,mt2701-m4u # mt2701 generation one HW
> > + - mediatek,mt2712-m4u # mt2712 generation two HW
> > + - mediatek,mt6779-m4u # mt6779 generation two HW
> > + - mediatek,mt8173-m4u # mt8173 generation two HW
> > + - mediatek,mt8183-m4u # mt8183 generation two HW
> > +
> > + - description: mt7623 generation one HW
> > + items:
> > + - const: mediatek,mt7623-m4u
> > + - const: mediatek,mt2701-m4u
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + description: |
> > + bclk is optional. here is the list which require this bclk:
> > + mt2701, mt2712, mt7623 and mt8173.
>
> Similarly to my comment in other patch, this should be part of schema
> within 'if-then'.
Thanks for the review.
I will change like this:
=============
clocks:
items:
- description: bclk is the block clock.
clock-names:
items:
- const: bclk
required:
- compatible
- reg
- interrupts
- mediatek,larbs
- '#iommu-cells'
if:
properties:
compatible:
contains:
enum:
- mediatek,mt2701-m4u
- mediatek,mt2712-m4u
- mediatek,mt8173-m4u
then:
required:
- clocks
==============
If this is not right, please tell me.
(dt_binding_check is ok.)
>
> Best regards,
> Krzysztof
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema
2020-10-06 4:26 ` Yong Wu
@ 2020-10-12 17:08 ` Krzysztof Kozlowski
2020-10-13 7:53 ` Yong Wu
0 siblings, 1 reply; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-12 17:08 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Tue, 6 Oct 2020 at 06:27, Yong Wu <yong.wu@mediatek.com> wrote:
>
> On Fri, 2020-10-02 at 13:07 +0200, Krzysztof Kozlowski wrote:
> > On Wed, Sep 30, 2020 at 03:06:24PM +0800, Yong Wu wrote:
> > > Convert MediaTek IOMMU to DT schema.
> > >
> > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > ---
> > > .../bindings/iommu/mediatek,iommu.txt | 103 ------------
> > > .../bindings/iommu/mediatek,iommu.yaml | 154 ++++++++++++++++++
> > > 2 files changed, 154 insertions(+), 103 deletions(-)
> > > delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> > > create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > >
>
> [...]
>
> > > +properties:
> > > + compatible:
> > > + oneOf:
> > > + - enum:
> > > + - mediatek,mt2701-m4u # mt2701 generation one HW
> > > + - mediatek,mt2712-m4u # mt2712 generation two HW
> > > + - mediatek,mt6779-m4u # mt6779 generation two HW
> > > + - mediatek,mt8173-m4u # mt8173 generation two HW
> > > + - mediatek,mt8183-m4u # mt8183 generation two HW
> > > +
> > > + - description: mt7623 generation one HW
> > > + items:
> > > + - const: mediatek,mt7623-m4u
> > > + - const: mediatek,mt2701-m4u
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + interrupts:
> > > + maxItems: 1
> > > +
> > > + clocks:
> > > + description: |
> > > + bclk is optional. here is the list which require this bclk:
> > > + mt2701, mt2712, mt7623 and mt8173.
> >
> > Similarly to my comment in other patch, this should be part of schema
> > within 'if-then'.
>
> Thanks for the review.
>
> I will change like this:
>
> =============
> clocks:
> items:
> - description: bclk is the block clock.
>
> clock-names:
> items:
> - const: bclk
>
> required:
> - compatible
> - reg
> - interrupts
> - mediatek,larbs
> - '#iommu-cells'
> if:
> properties:
> compatible:
> contains:
> enum:
> - mediatek,mt2701-m4u
> - mediatek,mt2712-m4u
> - mediatek,mt8173-m4u
>
> then:
> required:
> - clocks
> ==============
>
> If this is not right, please tell me.
> (dt_binding_check is ok.)
Looks fine, except "if" should be part of some "allOf" block.
Best regards,
Krzysztof
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema
2020-10-12 17:08 ` Krzysztof Kozlowski
@ 2020-10-13 7:53 ` Yong Wu
0 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-10-13 7:53 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Mon, 2020-10-12 at 19:08 +0200, Krzysztof Kozlowski wrote:
> On Tue, 6 Oct 2020 at 06:27, Yong Wu <yong.wu@mediatek.com> wrote:
> >
> > On Fri, 2020-10-02 at 13:07 +0200, Krzysztof Kozlowski wrote:
> > > On Wed, Sep 30, 2020 at 03:06:24PM +0800, Yong Wu wrote:
> > > > Convert MediaTek IOMMU to DT schema.
> > > >
> > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > > ---
> > > > .../bindings/iommu/mediatek,iommu.txt | 103 ------------
> > > > .../bindings/iommu/mediatek,iommu.yaml | 154 ++++++++++++++++++
> > > > 2 files changed, 154 insertions(+), 103 deletions(-)
> > > > delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> > > > create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > > >
> >
> > [...]
> >
> > > > +properties:
> > > > + compatible:
> > > > + oneOf:
> > > > + - enum:
> > > > + - mediatek,mt2701-m4u # mt2701 generation one HW
> > > > + - mediatek,mt2712-m4u # mt2712 generation two HW
> > > > + - mediatek,mt6779-m4u # mt6779 generation two HW
> > > > + - mediatek,mt8173-m4u # mt8173 generation two HW
> > > > + - mediatek,mt8183-m4u # mt8183 generation two HW
> > > > +
> > > > + - description: mt7623 generation one HW
> > > > + items:
> > > > + - const: mediatek,mt7623-m4u
> > > > + - const: mediatek,mt2701-m4u
> > > > +
> > > > + reg:
> > > > + maxItems: 1
> > > > +
> > > > + interrupts:
> > > > + maxItems: 1
> > > > +
> > > > + clocks:
> > > > + description: |
> > > > + bclk is optional. here is the list which require this bclk:
> > > > + mt2701, mt2712, mt7623 and mt8173.
> > >
> > > Similarly to my comment in other patch, this should be part of schema
> > > within 'if-then'.
> >
> > Thanks for the review.
> >
> > I will change like this:
> >
> > =============
> > clocks:
> > items:
> > - description: bclk is the block clock.
> >
> > clock-names:
> > items:
> > - const: bclk
> >
> > required:
> > - compatible
> > - reg
> > - interrupts
> > - mediatek,larbs
> > - '#iommu-cells'
> > if:
> > properties:
> > compatible:
> > contains:
> > enum:
> > - mediatek,mt2701-m4u
> > - mediatek,mt2712-m4u
> > - mediatek,mt8173-m4u
> >
> > then:
> > required:
> > - clocks
> > ==============
> >
> > If this is not right, please tell me.
> > (dt_binding_check is ok.)
>
> Looks fine, except "if" should be part of some "allOf" block.
Thanks very much for the review.
I will add "allOf" in next version.
>
> Best regards,
> Krzysztof
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI to DT schema
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
2020-09-30 7:06 ` [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-10-02 11:04 ` Krzysztof Kozlowski
2020-10-02 11:08 ` Krzysztof Kozlowski
2020-09-30 7:06 ` [PATCH v3 03/24] dt-bindings: memory: mediatek: Add a common larb-port header file Yong Wu
` (22 subsequent siblings)
24 siblings, 2 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Convert MediaTek SMI to DT schema.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
.../mediatek,smi-common.txt | 49 ---------
.../mediatek,smi-common.yaml | 100 ++++++++++++++++++
.../memory-controllers/mediatek,smi-larb.txt | 49 ---------
.../memory-controllers/mediatek,smi-larb.yaml | 91 ++++++++++++++++
4 files changed, 191 insertions(+), 98 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
deleted file mode 100644
index b64573680b42..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-SMI (Smart Multimedia Interface) Common
-
-The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
-
-Mediatek SMI have two generations of HW architecture, here is the list
-which generation the SoCs use:
-generation 1: mt2701 and mt7623.
-generation 2: mt2712, mt6779, mt8173 and mt8183.
-
-There's slight differences between the two SMI, for generation 2, the
-register which control the iommu port is at each larb's register base. But
-for generation 1, the register is at smi ao base(smi always on register
-base). Besides that, the smi async clock should be prepared and enabled for
-SMI generation 1 to transform the smi clock into emi clock domain, but that is
-not needed for SMI generation 2.
-
-Required properties:
-- compatible : must be one of :
- "mediatek,mt2701-smi-common"
- "mediatek,mt2712-smi-common"
- "mediatek,mt6779-smi-common"
- "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
- "mediatek,mt8173-smi-common"
- "mediatek,mt8183-smi-common"
-- reg : the register and size of the SMI block.
-- power-domains : a phandle to the power domain of this local arbiter.
-- clocks : Must contain an entry for each entry in clock-names.
-- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
- for generation 2 smi HW as follows:
- - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
- the register.
- - "smi" : It's the clock for transfer data and command.
- They may be the same if both source clocks are the same.
- - "async" : asynchronous clock, it help transform the smi clock into the emi
- clock domain, this clock is only needed by generation 1 smi HW.
- and these 2 option clocks for generation 2 smi HW:
- - "gals0": the path0 clock of GALS(Global Async Local Sync).
- - "gals1": the path1 clock of GALS(Global Async Local Sync).
- Here is the list which has this GALS: mt6779 and mt8183.
-
-Example:
- smi_common: smi@14022000 {
- compatible = "mediatek,mt8173-smi-common";
- reg = <0 0x14022000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_SMI_COMMON>,
- <&mmsys CLK_MM_SMI_COMMON>;
- clock-names = "apb", "smi";
- };
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
new file mode 100644
index 000000000000..76ecc7205438
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SMI (Smart Multimedia Interface) Common
+
+maintainers:
+ - Yong Wu <yong.wu@mediatek.com>
+
+description: |+
+ The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
+
+ MediaTek SMI have two generations of HW architecture, here is the list
+ which generation the SoCs use:
+ generation 1: mt2701 and mt7623.
+ generation 2: mt2712, mt6779, mt8173 and mt8183.
+
+ There's slight differences between the two SMI, for generation 2, the
+ register which control the iommu port is at each larb's register base. But
+ for generation 1, the register is at smi ao base(smi always on register
+ base). Besides that, the smi async clock should be prepared and enabled for
+ SMI generation 1 to transform the smi clock into emi clock domain, but that is
+ not needed for SMI generation 2.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt2701-smi-common
+ - mediatek,mt2712-smi-common
+ - mediatek,mt6779-smi-common
+ - mediatek,mt8173-smi-common
+ - mediatek,mt8183-smi-common
+
+ - description: for mt7623
+ items:
+ - const: mediatek,mt7623-smi-common
+ - const: mediatek,mt2701-smi-common
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: |
+ apb and smi are mandatory. the async is only for generation 1 smi HW.
+ gals(global async local sync) also is optional, here is the list which
+ require gals: mt6779 and mt8183.
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: apb is Advanced Peripheral Bus clock, It's the clock for
+ setting the register.
+ - description: smi is the clock for transfer data and command.
+ - description: async is asynchronous clock, it help transform the smi clock
+ into the emi clock domain.
+ - description: gals0 is the path0 clock of gals.
+ - description: gals1 is the path1 clock of gals.
+
+ clock-names:
+ oneOf:
+ - items:
+ - const: apb
+ - const: smi
+ - items:
+ - const: apb
+ - const: smi
+ - const: async
+ - items:
+ - const: apb
+ - const: smi
+ - const: gals0
+ - const: gals1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ smi_common: smi@14022000 {
+ compatible = "mediatek,mt8173-smi-common";
+ reg = <0x14022000 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_COMMON>;
+ clock-names = "apb", "smi";
+ };
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
deleted file mode 100644
index 8f19dfe7d80e..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-SMI (Smart Multimedia Interface) Local Arbiter
-
-The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
-
-Required properties:
-- compatible : must be one of :
- "mediatek,mt2701-smi-larb"
- "mediatek,mt2712-smi-larb"
- "mediatek,mt6779-smi-larb"
- "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
- "mediatek,mt8173-smi-larb"
- "mediatek,mt8183-smi-larb"
-- reg : the register and size of this local arbiter.
-- mediatek,smi : a phandle to the smi_common node.
-- power-domains : a phandle to the power domain of this local arbiter.
-- clocks : Must contain an entry for each entry in clock-names.
-- clock-names: must contain 2 entries, as follows:
- - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
- the register.
- - "smi" : It's the clock for transfer data and command.
- and this optional clock name:
- - "gals": the clock for GALS(Global Async Local Sync).
- Here is the list which has this GALS: mt8183.
-
-Required property for mt2701, mt2712, mt6779 and mt7623:
-- mediatek,larb-id :the hardware id of this larb.
-
-Example:
- larb1: larb@16010000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x16010000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
- clocks = <&vdecsys CLK_VDEC_CKEN>,
- <&vdecsys CLK_VDEC_LARB_CKEN>;
- clock-names = "apb", "smi";
- };
-
-Example for mt2701:
- larb0: larb@14010000 {
- compatible = "mediatek,mt2701-smi-larb";
- reg = <0 0x14010000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- mediatek,larb-id = <0>;
- clocks = <&mmsys CLK_MM_SMI_LARB0>,
- <&mmsys CLK_MM_SMI_LARB0>;
- clock-names = "apb", "smi";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
- };
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
new file mode 100644
index 000000000000..50793a0e6759
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SMI (Smart Multimedia Interface) Local Arbiter
+
+maintainers:
+ - Yong Wu <yong.wu@mediatek.com>
+
+description: |+
+ The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt2701-smi-larb
+ - mediatek,mt2712-smi-larb
+ - mediatek,mt6779-smi-larb
+ - mediatek,mt8173-smi-larb
+ - mediatek,mt8183-smi-larb
+
+ - description: for mt7623
+ items:
+ - const: mediatek,mt7623-smi-larb
+ - const: mediatek,mt2701-smi-larb
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: |
+ apb and smi are mandatory. gals(global async local sync) is optional,
+ here is the list which require gals: mt8183.
+ minItems: 2
+ maxItems: 3
+ items:
+ - description: apb is Advanced Peripheral Bus clock, It's the clock for
+ setting the register.
+ - description: smi is the clock for transfer data and command.
+ - description: the clock for gals.
+
+ clock-names:
+ oneOf:
+ - items:
+ - const: apb
+ - const: smi
+ - items:
+ - const: apb
+ - const: smi
+ - const: gals
+
+ power-domains:
+ maxItems: 1
+
+ mediatek,smi:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: a phandle to the smi_common node.
+
+ mediatek,larb-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 15
+ description: the hardware id of this larb.
+ Required property for mt2701, mt2712, mt6779 and mt7623.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ larb1: larb@16010000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0x16010000 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
+ clocks = <&vdecsys CLK_VDEC_CKEN>,
+ <&vdecsys CLK_VDEC_LARB_CKEN>;
+ clock-names = "apb", "smi";
+ };
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI to DT schema
2020-09-30 7:06 ` [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI " Yong Wu
@ 2020-10-02 11:04 ` Krzysztof Kozlowski
2020-10-02 11:08 ` Krzysztof Kozlowski
1 sibling, 0 replies; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-02 11:04 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> Convert MediaTek SMI to DT schema.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> .../mediatek,smi-common.txt | 49 ---------
> .../mediatek,smi-common.yaml | 100 ++++++++++++++++++
> .../memory-controllers/mediatek,smi-larb.txt | 49 ---------
> .../memory-controllers/mediatek,smi-larb.yaml | 91 ++++++++++++++++
> 4 files changed, 191 insertions(+), 98 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> deleted file mode 100644
> index b64573680b42..000000000000
> --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> +++ /dev/null
> @@ -1,49 +0,0 @@
> -SMI (Smart Multimedia Interface) Common
> -
> -The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
> -
> -Mediatek SMI have two generations of HW architecture, here is the list
> -which generation the SoCs use:
> -generation 1: mt2701 and mt7623.
> -generation 2: mt2712, mt6779, mt8173 and mt8183.
> -
> -There's slight differences between the two SMI, for generation 2, the
> -register which control the iommu port is at each larb's register base. But
> -for generation 1, the register is at smi ao base(smi always on register
> -base). Besides that, the smi async clock should be prepared and enabled for
> -SMI generation 1 to transform the smi clock into emi clock domain, but that is
> -not needed for SMI generation 2.
> -
> -Required properties:
> -- compatible : must be one of :
> - "mediatek,mt2701-smi-common"
> - "mediatek,mt2712-smi-common"
> - "mediatek,mt6779-smi-common"
> - "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
> - "mediatek,mt8173-smi-common"
> - "mediatek,mt8183-smi-common"
> -- reg : the register and size of the SMI block.
> -- power-domains : a phandle to the power domain of this local arbiter.
> -- clocks : Must contain an entry for each entry in clock-names.
> -- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
> - for generation 2 smi HW as follows:
> - - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
> - the register.
> - - "smi" : It's the clock for transfer data and command.
> - They may be the same if both source clocks are the same.
> - - "async" : asynchronous clock, it help transform the smi clock into the emi
> - clock domain, this clock is only needed by generation 1 smi HW.
> - and these 2 option clocks for generation 2 smi HW:
> - - "gals0": the path0 clock of GALS(Global Async Local Sync).
> - - "gals1": the path1 clock of GALS(Global Async Local Sync).
> - Here is the list which has this GALS: mt6779 and mt8183.
> -
> -Example:
> - smi_common: smi@14022000 {
> - compatible = "mediatek,mt8173-smi-common";
> - reg = <0 0x14022000 0 0x1000>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_SMI_COMMON>,
> - <&mmsys CLK_MM_SMI_COMMON>;
> - clock-names = "apb", "smi";
> - };
> diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> new file mode 100644
> index 000000000000..76ecc7205438
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
You relicense existing GPLv2 work. Please CC all contributors and
collect their acks/SoB.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SMI (Smart Multimedia Interface) Common
> +
> +maintainers:
> + - Yong Wu <yong.wu@mediatek.com>
> +
> +description: |+
> + The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
> +
> + MediaTek SMI have two generations of HW architecture, here is the list
> + which generation the SoCs use:
> + generation 1: mt2701 and mt7623.
> + generation 2: mt2712, mt6779, mt8173 and mt8183.
> +
> + There's slight differences between the two SMI, for generation 2, the
> + register which control the iommu port is at each larb's register base. But
> + for generation 1, the register is at smi ao base(smi always on register
> + base). Besides that, the smi async clock should be prepared and enabled for
> + SMI generation 1 to transform the smi clock into emi clock domain, but that is
> + not needed for SMI generation 2.
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - mediatek,mt2701-smi-common
> + - mediatek,mt2712-smi-common
> + - mediatek,mt6779-smi-common
> + - mediatek,mt8173-smi-common
> + - mediatek,mt8183-smi-common
> +
> + - description: for mt7623
> + items:
> + - const: mediatek,mt7623-smi-common
> + - const: mediatek,mt2701-smi-common
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + description: |
> + apb and smi are mandatory. the async is only for generation 1 smi HW.
> + gals(global async local sync) also is optional, here is the list which
> + require gals: mt6779 and mt8183.
> + minItems: 2
> + maxItems: 4
> + items:
> + - description: apb is Advanced Peripheral Bus clock, It's the clock for
> + setting the register.
> + - description: smi is the clock for transfer data and command.
> + - description: async is asynchronous clock, it help transform the smi clock
> + into the emi clock domain.
> + - description: gals0 is the path0 clock of gals.
> + - description: gals1 is the path1 clock of gals.
You put here five items, but max are four. Does it really work as
intended?
> +
> + clock-names:
> + oneOf:
> + - items:
> + - const: apb
> + - const: smi
> + - items:
> + - const: apb
> + - const: smi
> + - const: async
> + - items:
> + - const: apb
> + - const: smi
> + - const: gals0
> + - const: gals1
> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8173-clk.h>
> + #include <dt-bindings/power/mt8173-power.h>
> +
> + smi_common: smi@14022000 {
> + compatible = "mediatek,mt8173-smi-common";
> + reg = <0x14022000 0x1000>;
> + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_SMI_COMMON>,
> + <&mmsys CLK_MM_SMI_COMMON>;
> + clock-names = "apb", "smi";
> + };
> diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> deleted file mode 100644
> index 8f19dfe7d80e..000000000000
> --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> +++ /dev/null
> @@ -1,49 +0,0 @@
> -SMI (Smart Multimedia Interface) Local Arbiter
> -
> -The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
> -
> -Required properties:
> -- compatible : must be one of :
> - "mediatek,mt2701-smi-larb"
> - "mediatek,mt2712-smi-larb"
> - "mediatek,mt6779-smi-larb"
> - "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
> - "mediatek,mt8173-smi-larb"
> - "mediatek,mt8183-smi-larb"
> -- reg : the register and size of this local arbiter.
> -- mediatek,smi : a phandle to the smi_common node.
> -- power-domains : a phandle to the power domain of this local arbiter.
> -- clocks : Must contain an entry for each entry in clock-names.
> -- clock-names: must contain 2 entries, as follows:
> - - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
> - the register.
> - - "smi" : It's the clock for transfer data and command.
> - and this optional clock name:
> - - "gals": the clock for GALS(Global Async Local Sync).
> - Here is the list which has this GALS: mt8183.
> -
> -Required property for mt2701, mt2712, mt6779 and mt7623:
> -- mediatek,larb-id :the hardware id of this larb.
> -
> -Example:
> - larb1: larb@16010000 {
> - compatible = "mediatek,mt8173-smi-larb";
> - reg = <0 0x16010000 0 0x1000>;
> - mediatek,smi = <&smi_common>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
> - clocks = <&vdecsys CLK_VDEC_CKEN>,
> - <&vdecsys CLK_VDEC_LARB_CKEN>;
> - clock-names = "apb", "smi";
> - };
> -
> -Example for mt2701:
> - larb0: larb@14010000 {
> - compatible = "mediatek,mt2701-smi-larb";
> - reg = <0 0x14010000 0 0x1000>;
> - mediatek,smi = <&smi_common>;
> - mediatek,larb-id = <0>;
> - clocks = <&mmsys CLK_MM_SMI_LARB0>,
> - <&mmsys CLK_MM_SMI_LARB0>;
> - clock-names = "apb", "smi";
> - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> - };
> diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> new file mode 100644
> index 000000000000..50793a0e6759
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> @@ -0,0 +1,91 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
The same - you need to collect licensing change agreements.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SMI (Smart Multimedia Interface) Local Arbiter
> +
> +maintainers:
> + - Yong Wu <yong.wu@mediatek.com>
> +
> +description: |+
> + The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - mediatek,mt2701-smi-larb
> + - mediatek,mt2712-smi-larb
> + - mediatek,mt6779-smi-larb
> + - mediatek,mt8173-smi-larb
> + - mediatek,mt8183-smi-larb
> +
> + - description: for mt7623
> + items:
> + - const: mediatek,mt7623-smi-larb
> + - const: mediatek,mt2701-smi-larb
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + description: |
> + apb and smi are mandatory. gals(global async local sync) is optional,
> + here is the list which require gals: mt8183.
> + minItems: 2
> + maxItems: 3
> + items:
> + - description: apb is Advanced Peripheral Bus clock, It's the clock for
> + setting the register.
> + - description: smi is the clock for transfer data and command.
> + - description: the clock for gals.
> +
> + clock-names:
> + oneOf:
> + - items:
> + - const: apb
> + - const: smi
> + - items:
> + - const: apb
> + - const: smi
> + - const: gals
> +
> + power-domains:
> + maxItems: 1
> +
> + mediatek,smi:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: a phandle to the smi_common node.
> +
> + mediatek,larb-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 15
> + description: the hardware id of this larb.
> + Required property for mt2701, mt2712, mt6779 and mt7623.
You need if-then-required for this. See
Documentation/devicetree/bindings/example-schema.yaml for example.
Best regards,
Krzysztof
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI to DT schema
2020-09-30 7:06 ` [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI " Yong Wu
2020-10-02 11:04 ` Krzysztof Kozlowski
@ 2020-10-02 11:08 ` Krzysztof Kozlowski
2020-10-06 4:27 ` Yong Wu
1 sibling, 1 reply; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-02 11:08 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> Convert MediaTek SMI to DT schema.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> .../mediatek,smi-common.txt | 49 ---------
> .../mediatek,smi-common.yaml | 100 ++++++++++++++++++
> .../memory-controllers/mediatek,smi-larb.txt | 49 ---------
> .../memory-controllers/mediatek,smi-larb.yaml | 91 ++++++++++++++++
> 4 files changed, 191 insertions(+), 98 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> deleted file mode 100644
> index b64573680b42..000000000000
> --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> +++ /dev/null
> @@ -1,49 +0,0 @@
> -SMI (Smart Multimedia Interface) Common
> -
> -The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
> -
> -Mediatek SMI have two generations of HW architecture, here is the list
> -which generation the SoCs use:
> -generation 1: mt2701 and mt7623.
> -generation 2: mt2712, mt6779, mt8173 and mt8183.
> -
> -There's slight differences between the two SMI, for generation 2, the
> -register which control the iommu port is at each larb's register base. But
> -for generation 1, the register is at smi ao base(smi always on register
> -base). Besides that, the smi async clock should be prepared and enabled for
> -SMI generation 1 to transform the smi clock into emi clock domain, but that is
> -not needed for SMI generation 2.
> -
> -Required properties:
> -- compatible : must be one of :
> - "mediatek,mt2701-smi-common"
> - "mediatek,mt2712-smi-common"
> - "mediatek,mt6779-smi-common"
> - "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
> - "mediatek,mt8173-smi-common"
> - "mediatek,mt8183-smi-common"
> -- reg : the register and size of the SMI block.
> -- power-domains : a phandle to the power domain of this local arbiter.
> -- clocks : Must contain an entry for each entry in clock-names.
> -- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
> - for generation 2 smi HW as follows:
> - - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
> - the register.
> - - "smi" : It's the clock for transfer data and command.
> - They may be the same if both source clocks are the same.
> - - "async" : asynchronous clock, it help transform the smi clock into the emi
> - clock domain, this clock is only needed by generation 1 smi HW.
> - and these 2 option clocks for generation 2 smi HW:
> - - "gals0": the path0 clock of GALS(Global Async Local Sync).
> - - "gals1": the path1 clock of GALS(Global Async Local Sync).
> - Here is the list which has this GALS: mt6779 and mt8183.
> -
> -Example:
> - smi_common: smi@14022000 {
> - compatible = "mediatek,mt8173-smi-common";
> - reg = <0 0x14022000 0 0x1000>;
> - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> - clocks = <&mmsys CLK_MM_SMI_COMMON>,
> - <&mmsys CLK_MM_SMI_COMMON>;
> - clock-names = "apb", "smi";
> - };
> diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> new file mode 100644
> index 000000000000..76ecc7205438
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SMI (Smart Multimedia Interface) Common
> +
> +maintainers:
> + - Yong Wu <yong.wu@mediatek.com>
> +
> +description: |+
> + The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
> +
> + MediaTek SMI have two generations of HW architecture, here is the list
> + which generation the SoCs use:
> + generation 1: mt2701 and mt7623.
> + generation 2: mt2712, mt6779, mt8173 and mt8183.
> +
> + There's slight differences between the two SMI, for generation 2, the
> + register which control the iommu port is at each larb's register base. But
> + for generation 1, the register is at smi ao base(smi always on register
> + base). Besides that, the smi async clock should be prepared and enabled for
> + SMI generation 1 to transform the smi clock into emi clock domain, but that is
> + not needed for SMI generation 2.
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - mediatek,mt2701-smi-common
> + - mediatek,mt2712-smi-common
> + - mediatek,mt6779-smi-common
> + - mediatek,mt8173-smi-common
> + - mediatek,mt8183-smi-common
> +
> + - description: for mt7623
> + items:
> + - const: mediatek,mt7623-smi-common
> + - const: mediatek,mt2701-smi-common
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + description: |
> + apb and smi are mandatory. the async is only for generation 1 smi HW.
> + gals(global async local sync) also is optional, here is the list which
> + require gals: mt6779 and mt8183.
> + minItems: 2
> + maxItems: 4
> + items:
> + - description: apb is Advanced Peripheral Bus clock, It's the clock for
> + setting the register.
> + - description: smi is the clock for transfer data and command.
> + - description: async is asynchronous clock, it help transform the smi clock
> + into the emi clock domain.
> + - description: gals0 is the path0 clock of gals.
> + - description: gals1 is the path1 clock of gals.
> +
> + clock-names:
> + oneOf:
> + - items:
> + - const: apb
> + - const: smi
> + - items:
> + - const: apb
> + - const: smi
> + - const: async
> + - items:
> + - const: apb
> + - const: smi
> + - const: gals0
> + - const: gals1
Similarly to my comment to other properties, this requirement per
compatible should be part of the schema within 'if-then'.
Best regards,
Krzysztof
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI to DT schema
2020-10-02 11:08 ` Krzysztof Kozlowski
@ 2020-10-06 4:27 ` Yong Wu
2020-10-06 7:15 ` Krzysztof Kozlowski
0 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-10-06 4:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Fri, 2020-10-02 at 13:08 +0200, Krzysztof Kozlowski wrote:
> On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> > Convert MediaTek SMI to DT schema.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> > .../mediatek,smi-common.txt | 49 ---------
> > .../mediatek,smi-common.yaml | 100 ++++++++++++++++++
> > .../memory-controllers/mediatek,smi-larb.txt | 49 ---------
> > .../memory-controllers/mediatek,smi-larb.yaml | 91 ++++++++++++++++
> > 4 files changed, 191 insertions(+), 98 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
...
> > +properties:
> > + compatible:
> > + oneOf:
> > + - enum:
> > + - mediatek,mt2701-smi-common
> > + - mediatek,mt2712-smi-common
> > + - mediatek,mt6779-smi-common
> > + - mediatek,mt8173-smi-common
> > + - mediatek,mt8183-smi-common
> > +
> > + - description: for mt7623
> > + items:
> > + - const: mediatek,mt7623-smi-common
> > + - const: mediatek,mt2701-smi-common
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + description: |
> > + apb and smi are mandatory. the async is only for generation 1 smi HW.
> > + gals(global async local sync) also is optional, here is the list which
> > + require gals: mt6779 and mt8183.
> > + minItems: 2
> > + maxItems: 4
> > + items:
> > + - description: apb is Advanced Peripheral Bus clock, It's the clock for
> > + setting the register.
> > + - description: smi is the clock for transfer data and command.
> > + - description: async is asynchronous clock, it help transform the smi clock
> > + into the emi clock domain.
> > + - description: gals0 is the path0 clock of gals.
> > + - description: gals1 is the path1 clock of gals.
> > +
> > + clock-names:
> > + oneOf:
> > + - items:
> > + - const: apb
> > + - const: smi
> > + - items:
> > + - const: apb
> > + - const: smi
> > + - const: async
> > + - items:
> > + - const: apb
> > + - const: smi
> > + - const: gals0
> > + - const: gals1
>
> Similarly to my comment to other properties, this requirement per
> compatible should be part of the schema within 'if-then'.
I'm not so familiar with this format. Do this has "if-then-'else
if'-then-else"?
I tried below instead of the clocks segment above:
===================================
if:
properties:
compatible:
enum:
- mediatek,mt6779-smi-common
- mediatek,mt8183-smi-common
then:
properties:
clock:
items:
- description: apb is the clock for setting the register..
- description: smi is the clock for transfer data and command.
- description: gals0 is the path0 clock of gals(global async
local sync).
- description: gals1 is the path1 clock of gals.
clock-names:
items:
- const: apb
- const: smi
- const: gals0
- const: gals1
else:
if:
properties:
compatible:
contains:
enum:
- mediatek,mt2701-smi-common
then:
properties:
clocks:
items:
- description: apb is the clock for setting the register.
- description: smi is the clock for transfer data and command.
- description: async is asynchronous clock, it help transform
the smi clock
into the emi clock domain.
clock-names:
items:
- const: apb
- const: smi
- const: async
else:
properties:
clocks:
items:
- description: apb is the clock for setting the register.
- description: smi is the clock for transfer data and
command.
clock-names:
items:
- const: apb
- const: smi
================================
But I got a warning when dt_binding_check:
CHKDT
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
SCHEMA
Documentation/devicetree/bindings/processed-schema-examples.yaml
DTC
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.example.dt.yaml
CHECK
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.example.dt.yaml
.../Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.example.dt.yaml: smi@14022000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
From
schema: .../Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
Any suggestion about this?
Thanks.
>
> Best regards,
> Krzysztof
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI to DT schema
2020-10-06 4:27 ` Yong Wu
@ 2020-10-06 7:15 ` Krzysztof Kozlowski
2020-10-10 6:18 ` Yong Wu
0 siblings, 1 reply; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-06 7:15 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Tue, 6 Oct 2020 at 06:27, Yong Wu <yong.wu@mediatek.com> wrote:
>
> On Fri, 2020-10-02 at 13:08 +0200, Krzysztof Kozlowski wrote:
> > On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> > > Convert MediaTek SMI to DT schema.
> > >
> > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > ---
> > > .../mediatek,smi-common.txt | 49 ---------
> > > .../mediatek,smi-common.yaml | 100 ++++++++++++++++++
> > > .../memory-controllers/mediatek,smi-larb.txt | 49 ---------
> > > .../memory-controllers/mediatek,smi-larb.yaml | 91 ++++++++++++++++
> > > 4 files changed, 191 insertions(+), 98 deletions(-)
> > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> ...
> > > +properties:
> > > + compatible:
> > > + oneOf:
> > > + - enum:
> > > + - mediatek,mt2701-smi-common
> > > + - mediatek,mt2712-smi-common
> > > + - mediatek,mt6779-smi-common
> > > + - mediatek,mt8173-smi-common
> > > + - mediatek,mt8183-smi-common
> > > +
> > > + - description: for mt7623
> > > + items:
> > > + - const: mediatek,mt7623-smi-common
> > > + - const: mediatek,mt2701-smi-common
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + clocks:
> > > + description: |
> > > + apb and smi are mandatory. the async is only for generation 1 smi HW.
> > > + gals(global async local sync) also is optional, here is the list which
> > > + require gals: mt6779 and mt8183.
> > > + minItems: 2
> > > + maxItems: 4
> > > + items:
> > > + - description: apb is Advanced Peripheral Bus clock, It's the clock for
> > > + setting the register.
> > > + - description: smi is the clock for transfer data and command.
> > > + - description: async is asynchronous clock, it help transform the smi clock
> > > + into the emi clock domain.
> > > + - description: gals0 is the path0 clock of gals.
> > > + - description: gals1 is the path1 clock of gals.
> > > +
> > > + clock-names:
> > > + oneOf:
> > > + - items:
> > > + - const: apb
> > > + - const: smi
> > > + - items:
> > > + - const: apb
> > > + - const: smi
> > > + - const: async
> > > + - items:
> > > + - const: apb
> > > + - const: smi
> > > + - const: gals0
> > > + - const: gals1
> >
> > Similarly to my comment to other properties, this requirement per
> > compatible should be part of the schema within 'if-then'.
>
> I'm not so familiar with this format. Do this has "if-then-'else
> if'-then-else"?
These are mutually exclusive conditions, so you can skip else:
- if-then
- if-then
- if-then
It will be more readable then stacking 'if' under 'else'
>
> I tried below instead of the clocks segment above:
>
> ===================================
> if:
> properties:
> compatible:
Missing contains. Just take an example from some existing schema.
> enum:
> - mediatek,mt6779-smi-common
> - mediatek,mt8183-smi-common
>
> then:
> properties:
> clock:
> items:
> - description: apb is the clock for setting the register..
> - description: smi is the clock for transfer data and command.
> - description: gals0 is the path0 clock of gals(global async
> local sync).
> - description: gals1 is the path1 clock of gals.
> clock-names:
> items:
> - const: apb
> - const: smi
> - const: gals0
> - const: gals1
> else:
> if:
> properties:
> compatible:
> contains:
> enum:
> - mediatek,mt2701-smi-common
>
> then:
> properties:
> clocks:
> items:
> - description: apb is the clock for setting the register.
> - description: smi is the clock for transfer data and command.
> - description: async is asynchronous clock, it help transform
> the smi clock
> into the emi clock domain.
> clock-names:
> items:
> - const: apb
> - const: smi
> - const: async
> else:
> properties:
> clocks:
> items:
> - description: apb is the clock for setting the register.
> - description: smi is the clock for transfer data and
> command.
> clock-names:
> items:
> - const: apb
> - const: smi
> ================================
>
> But I got a warning when dt_binding_check:
>
> CHKDT
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> SCHEMA
> Documentation/devicetree/bindings/processed-schema-examples.yaml
> DTC
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.example.dt.yaml
> CHECK
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.example.dt.yaml
> .../Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.example.dt.yaml: smi@14022000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
There are several files which already choose different clocks based on
compatible, simple grep shows them:
Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
Best regards,
Krzysztof
_______________________________________________
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iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI to DT schema
2020-10-06 7:15 ` Krzysztof Kozlowski
@ 2020-10-10 6:18 ` Yong Wu
2020-10-12 7:18 ` Krzysztof Kozlowski
0 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-10-10 6:18 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Tue, 2020-10-06 at 09:15 +0200, Krzysztof Kozlowski wrote:
> On Tue, 6 Oct 2020 at 06:27, Yong Wu <yong.wu@mediatek.com> wrote:
> >
> > On Fri, 2020-10-02 at 13:08 +0200, Krzysztof Kozlowski wrote:
> > > On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> > > > Convert MediaTek SMI to DT schema.
> > > >
> > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > > ---
> > > > .../mediatek,smi-common.txt | 49 ---------
> > > > .../mediatek,smi-common.yaml | 100 ++++++++++++++++++
> > > > .../memory-controllers/mediatek,smi-larb.txt | 49 ---------
> > > > .../memory-controllers/mediatek,smi-larb.yaml | 91 ++++++++++++++++
> > > > 4 files changed, 191 insertions(+), 98 deletions(-)
> > > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> > > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> > > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> > > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> > ...
> > > > +properties:
> > > > + compatible:
> > > > + oneOf:
> > > > + - enum:
> > > > + - mediatek,mt2701-smi-common
> > > > + - mediatek,mt2712-smi-common
> > > > + - mediatek,mt6779-smi-common
> > > > + - mediatek,mt8173-smi-common
> > > > + - mediatek,mt8183-smi-common
> > > > +
> > > > + - description: for mt7623
> > > > + items:
> > > > + - const: mediatek,mt7623-smi-common
> > > > + - const: mediatek,mt2701-smi-common
> > > > +
> > > > + reg:
> > > > + maxItems: 1
> > > > +
> > > > + clocks:
> > > > + description: |
> > > > + apb and smi are mandatory. the async is only for generation 1 smi HW.
> > > > + gals(global async local sync) also is optional, here is the list which
> > > > + require gals: mt6779 and mt8183.
> > > > + minItems: 2
> > > > + maxItems: 4
> > > > + items:
> > > > + - description: apb is Advanced Peripheral Bus clock, It's the clock for
> > > > + setting the register.
> > > > + - description: smi is the clock for transfer data and command.
> > > > + - description: async is asynchronous clock, it help transform the smi clock
> > > > + into the emi clock domain.
> > > > + - description: gals0 is the path0 clock of gals.
> > > > + - description: gals1 is the path1 clock of gals.
> > > > +
> > > > + clock-names:
> > > > + oneOf:
> > > > + - items:
> > > > + - const: apb
> > > > + - const: smi
> > > > + - items:
> > > > + - const: apb
> > > > + - const: smi
> > > > + - const: async
> > > > + - items:
> > > > + - const: apb
> > > > + - const: smi
> > > > + - const: gals0
> > > > + - const: gals1
> > >
> > > Similarly to my comment to other properties, this requirement per
> > > compatible should be part of the schema within 'if-then'.
> >
> > I'm not so familiar with this format. Do this has "if-then-'else
> > if'-then-else"?
>
> These are mutually exclusive conditions, so you can skip else:
> - if-then
> - if-then
> - if-then
> It will be more readable then stacking 'if' under 'else'
Thanks. I will use something like this:
anyOf:
- if: #gen1 hw
then:
use apb/smi/async clocks
- if: #gen2 hw that has gals.
then:
use apb/smi/gals0/gals1 clocks
else: # gen2 hw that doesn't have gals.
use apb/smi clocks.
>
> >
> > I tried below instead of the clocks segment above:
> >
> > ===================================
> > if:
> > properties:
> > compatible:
>
> Missing contains. Just take an example from some existing schema.
Like the example you gave below
(Documentation/devicetree/bindings/clock/idt,versaclock5.yaml), It also
doesn't have "contains" in "if". I guess it is unnecessary if there is
only one compatible string. it may be necessary when it has backward
compatible string.
>
> > enum:
> > - mediatek,mt6779-smi-common
> > - mediatek,mt8183-smi-common
> >
> > then:
> > properties:
> > clock:
> > items:
> > - description: apb is the clock for setting the register..
> > - description: smi is the clock for transfer data and command.
> > - description: gals0 is the path0 clock of gals(global async
> > local sync).
> > - description: gals1 is the path1 clock of gals.
> > clock-names:
> > items:
> > - const: apb
> > - const: smi
> > - const: gals0
> > - const: gals1
> > else:
> > if:
> > properties:
> > compatible:
> > contains:
> > enum:
> > - mediatek,mt2701-smi-common
> >
> > then:
> > properties:
> > clocks:
> > items:
> > - description: apb is the clock for setting the register.
> > - description: smi is the clock for transfer data and command.
> > - description: async is asynchronous clock, it help transform
> > the smi clock
> > into the emi clock domain.
> > clock-names:
> > items:
> > - const: apb
> > - const: smi
> > - const: async
> > else:
> > properties:
> > clocks:
> > items:
> > - description: apb is the clock for setting the register.
> > - description: smi is the clock for transfer data and
> > command.
> > clock-names:
> > items:
> > - const: apb
> > - const: smi
> > ================================
> >
> > But I got a warning when dt_binding_check:
> >
> > CHKDT
> > Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> > SCHEMA
> > Documentation/devicetree/bindings/processed-schema-examples.yaml
> > DTC
> > Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.example.dt.yaml
> > CHECK
> > Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.example.dt.yaml
> > .../Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.example.dt.yaml: smi@14022000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
>
> There are several files which already choose different clocks based on
> compatible, simple grep shows them:
> Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
> Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
Thanks for the review. I will send the next version after v5.10.
>
> Best regards,
> Krzysztof
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI to DT schema
2020-10-10 6:18 ` Yong Wu
@ 2020-10-12 7:18 ` Krzysztof Kozlowski
2020-10-12 12:01 ` Yong Wu
0 siblings, 1 reply; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-12 7:18 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Sat, Oct 10, 2020 at 02:18:11PM +0800, Yong Wu wrote:
> On Tue, 2020-10-06 at 09:15 +0200, Krzysztof Kozlowski wrote:
> > On Tue, 6 Oct 2020 at 06:27, Yong Wu <yong.wu@mediatek.com> wrote:
> > >
> > > On Fri, 2020-10-02 at 13:08 +0200, Krzysztof Kozlowski wrote:
> > > > On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> > > > > Convert MediaTek SMI to DT schema.
> > > > >
> > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > > > ---
> > > > > .../mediatek,smi-common.txt | 49 ---------
> > > > > .../mediatek,smi-common.yaml | 100 ++++++++++++++++++
> > > > > .../memory-controllers/mediatek,smi-larb.txt | 49 ---------
> > > > > .../memory-controllers/mediatek,smi-larb.yaml | 91 ++++++++++++++++
> > > > > 4 files changed, 191 insertions(+), 98 deletions(-)
> > > > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> > > > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> > > > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> > > > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> > > ...
> > > > > +properties:
> > > > > + compatible:
> > > > > + oneOf:
> > > > > + - enum:
> > > > > + - mediatek,mt2701-smi-common
> > > > > + - mediatek,mt2712-smi-common
> > > > > + - mediatek,mt6779-smi-common
> > > > > + - mediatek,mt8173-smi-common
> > > > > + - mediatek,mt8183-smi-common
> > > > > +
> > > > > + - description: for mt7623
> > > > > + items:
> > > > > + - const: mediatek,mt7623-smi-common
> > > > > + - const: mediatek,mt2701-smi-common
> > > > > +
> > > > > + reg:
> > > > > + maxItems: 1
> > > > > +
> > > > > + clocks:
> > > > > + description: |
> > > > > + apb and smi are mandatory. the async is only for generation 1 smi HW.
> > > > > + gals(global async local sync) also is optional, here is the list which
> > > > > + require gals: mt6779 and mt8183.
> > > > > + minItems: 2
> > > > > + maxItems: 4
> > > > > + items:
> > > > > + - description: apb is Advanced Peripheral Bus clock, It's the clock for
> > > > > + setting the register.
> > > > > + - description: smi is the clock for transfer data and command.
> > > > > + - description: async is asynchronous clock, it help transform the smi clock
> > > > > + into the emi clock domain.
> > > > > + - description: gals0 is the path0 clock of gals.
> > > > > + - description: gals1 is the path1 clock of gals.
> > > > > +
> > > > > + clock-names:
> > > > > + oneOf:
> > > > > + - items:
> > > > > + - const: apb
> > > > > + - const: smi
> > > > > + - items:
> > > > > + - const: apb
> > > > > + - const: smi
> > > > > + - const: async
> > > > > + - items:
> > > > > + - const: apb
> > > > > + - const: smi
> > > > > + - const: gals0
> > > > > + - const: gals1
> > > >
> > > > Similarly to my comment to other properties, this requirement per
> > > > compatible should be part of the schema within 'if-then'.
> > >
> > > I'm not so familiar with this format. Do this has "if-then-'else
> > > if'-then-else"?
> >
> > These are mutually exclusive conditions, so you can skip else:
> > - if-then
> > - if-then
> > - if-then
> > It will be more readable then stacking 'if' under 'else'
>
> Thanks. I will use something like this:
>
> anyOf:
Then it should be oneOf as only one condition can be valid.
Best regards,
Krzysztof
> - if: #gen1 hw
> then:
> use apb/smi/async clocks
>
> - if: #gen2 hw that has gals.
> then:
> use apb/smi/gals0/gals1 clocks
> else: # gen2 hw that doesn't have gals.
> use apb/smi clocks.
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI to DT schema
2020-10-12 7:18 ` Krzysztof Kozlowski
@ 2020-10-12 12:01 ` Yong Wu
2020-10-12 13:26 ` Krzysztof Kozlowski
0 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-10-12 12:01 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Herring
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Mon, 2020-10-12 at 09:18 +0200, Krzysztof Kozlowski wrote:
> On Sat, Oct 10, 2020 at 02:18:11PM +0800, Yong Wu wrote:
> > On Tue, 2020-10-06 at 09:15 +0200, Krzysztof Kozlowski wrote:
> > > On Tue, 6 Oct 2020 at 06:27, Yong Wu <yong.wu@mediatek.com> wrote:
> > > >
> > > > On Fri, 2020-10-02 at 13:08 +0200, Krzysztof Kozlowski wrote:
> > > > > On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> > > > > > Convert MediaTek SMI to DT schema.
> > > > > >
> > > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > > > > ---
> > > > > > .../mediatek,smi-common.txt | 49 ---------
> > > > > > .../mediatek,smi-common.yaml | 100 ++++++++++++++++++
> > > > > > .../memory-controllers/mediatek,smi-larb.txt | 49 ---------
> > > > > > .../memory-controllers/mediatek,smi-larb.yaml | 91 ++++++++++++++++
> > > > > > 4 files changed, 191 insertions(+), 98 deletions(-)
> > > > > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> > > > > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> > > > > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> > > > > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> > > > ...
> > > > > > +properties:
> > > > > > + compatible:
> > > > > > + oneOf:
> > > > > > + - enum:
> > > > > > + - mediatek,mt2701-smi-common
> > > > > > + - mediatek,mt2712-smi-common
> > > > > > + - mediatek,mt6779-smi-common
> > > > > > + - mediatek,mt8173-smi-common
> > > > > > + - mediatek,mt8183-smi-common
> > > > > > +
> > > > > > + - description: for mt7623
> > > > > > + items:
> > > > > > + - const: mediatek,mt7623-smi-common
> > > > > > + - const: mediatek,mt2701-smi-common
> > > > > > +
> > > > > > + reg:
> > > > > > + maxItems: 1
> > > > > > +
> > > > > > + clocks:
> > > > > > + description: |
> > > > > > + apb and smi are mandatory. the async is only for generation 1 smi HW.
> > > > > > + gals(global async local sync) also is optional, here is the list which
> > > > > > + require gals: mt6779 and mt8183.
> > > > > > + minItems: 2
> > > > > > + maxItems: 4
> > > > > > + items:
> > > > > > + - description: apb is Advanced Peripheral Bus clock, It's the clock for
> > > > > > + setting the register.
> > > > > > + - description: smi is the clock for transfer data and command.
> > > > > > + - description: async is asynchronous clock, it help transform the smi clock
> > > > > > + into the emi clock domain.
> > > > > > + - description: gals0 is the path0 clock of gals.
> > > > > > + - description: gals1 is the path1 clock of gals.
> > > > > > +
> > > > > > + clock-names:
> > > > > > + oneOf:
> > > > > > + - items:
> > > > > > + - const: apb
> > > > > > + - const: smi
> > > > > > + - items:
> > > > > > + - const: apb
> > > > > > + - const: smi
> > > > > > + - const: async
> > > > > > + - items:
> > > > > > + - const: apb
> > > > > > + - const: smi
> > > > > > + - const: gals0
> > > > > > + - const: gals1
> > > > >
> > > > > Similarly to my comment to other properties, this requirement per
> > > > > compatible should be part of the schema within 'if-then'.
> > > >
> > > > I'm not so familiar with this format. Do this has "if-then-'else
> > > > if'-then-else"?
> > >
> > > These are mutually exclusive conditions, so you can skip else:
> > > - if-then
> > > - if-then
> > > - if-then
> > > It will be more readable then stacking 'if' under 'else'
> >
> > Thanks. I will use something like this:
> >
> > anyOf:
>
> Then it should be oneOf as only one condition can be valid.
I did do this at the beginning. But I get a warning log when
dt_binding_check.
Below is my schema and the detailed warning log:
//=======================================
clocks:
description: |
xxxxx
minItems: 2
maxItems: 4
items:
- description: apb is the clock for setting the register.
- description: smi is the clock for transfer data and command.
- description: async is asynchronous clock.
- description: gals0 is the path0 clock of gals.
- description: gals1 is the path1 clock of gals.
clock-names:
minItems: 2
maxItems: 4
required:
- compatible
- reg
- power-domains
- clocks
- clock-names
oneOf:
- if: #only for gen1 HW
properties:
compatible:
contains:
enum:
- mediatek,mt2701-smi-common
then:
properties:
clock:
items:
minItems: 3
maxItems: 3
clock-names:
items:
- const: apb
- const: smi
- const: async
- if: #for gen2 HW that have gals
properties:
compatible:
enum:
- mediatek,mt6779-smi-common
- mediatek,mt8183-smi-common
- mediatek,mt8192-smi-common
then:
properties:
clock:
items:
minItems: 4
maxItems: 4
clock-names:
items:
- const: apb
- const: smi
- const: gals0
- const: gals1
else: #for gen2 HW that don't have gals
properties:
clock:
items:
minItems: 2
maxItems: 2
clock-names:
items:
- const: apb
- const: smi
additionalProperties: false
//===========warning log=====================
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.example.dt.yaml
.../Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.example.dt.yaml: smi@14022000: {'compatible': ['mediatek,mt8173-smi-common'], 'reg': [[335683584, 4096]], 'power-domains': [[4294967295, 3]], 'clocks': [[4294967295, 1], [4294967295, 1]], 'clock-names': ['apb', 'smi'], '$nodename': ['smi@14022000']} is valid under each of {'else': {'properties': {'clock': {'items': {'maxItems': 2, 'minItems': 2}, 'type': 'array'}, 'clock-names': {'additionalItems': False, 'items': [{'const': 'apb'}, {'const': 'smi'}], 'maxItems': 2, 'minItems': 2, 'type': 'array'}}}, 'if': {'properties': {'compatible': {'additionalItems': False, 'items': [{'enum': ['mediatek,mt6779-smi-common', 'mediatek,mt8183-smi-common', 'mediatek,mt8192-smi-common']}], 'maxItems': 1, 'minItems': 1, 'type': 'array'}}}, 'then': {'properties': {'clock': {'items': {'maxItems': 4, 'minItems': 4}, 'type': 'array'}, 'clock-names': {'additionalItems': False, 'items': [{'const': 'apb'}, {'const': 'smi'}, {'const'
: 'gals0'}, {'const': 'gals1'}], 'maxItems': 4, 'minItems': 4, 'type': 'array'}}}}, {'if': {'properties': {'compatible': {'contains': {'enum': ['mediatek,mt2701-smi-common']}}}}, 'then': {'properties': {'clock': {'items': {'maxItems': 3, 'minItems': 3}, 'type': 'array'}, 'clock-names': {'additionalItems': False, 'items': [{'const': 'apb'}, {'const': 'smi'}, {'const': 'async'}], 'maxItems': 3, 'minItems': 3, 'type': 'array'}}}}
{'$filename':
'.../Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml',
'$id':
'http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#',
'$schema': 'http://devicetree.org/meta-schemas/core.yaml#',
'$select_validator': <jsonschema.validators.create.<locals>.Validator
object at 0x7fb3df378908>,
'additionalProperties': False,
'oneOf': [{'if': {'properties': {'compatible': {'contains': {'enum':
['mediatek,mt2701-smi-common']}}}},
'then': {'properties': {'clock': {'items': {'maxItems': 3,
'minItems': 3},
'type': 'array'},
'clock-names': {'additionalItems':
False,
'items': [{'const':
'apb'},
{'const':
'smi'},
{'const':
'async'}],
'maxItems': 3,
'minItems': 3,
'type': 'array'}}}},
{'else': {'properties': {'clock': {'items': {'maxItems': 2,
'minItems': 2},
'type': 'array'},
'clock-names': {'additionalItems':
False,
'items': [{'const':
'apb'},
{'const':
'smi'}],
'maxItems': 2,
'minItems': 2,
'type': 'array'}}},
'if': {'properties': {'compatible': {'additionalItems':
False,
'items': [{'enum':
['mediatek,mt6779-smi-common',
'mediatek,mt8183-smi-common',
'mediatek,mt8192-smi-common']}],
'maxItems': 1,
'minItems': 1,
'type': 'array'}}},
'then': {'properties': {'clock': {'items': {'maxItems': 4,
'minItems': 4},
'type': 'array'},
'clock-names': {'additionalItems':
False,
'items': [{'const':
'apb'},
{'const':
'smi'},
{'const':
'gals0'},
{'const':
'gals1'}],
'maxItems': 4,
'minItems': 4,
'type':
'array'}}}}],
'patternProperties': {'pinctrl-[0-9]+': True},
'properties': {'$nodename': True,
'clock-names': {'maxItems': 4, 'minItems': 2},
'clocks': {'additionalItems': False,
'items': [{}, {}, {}, {}, {}],
'maxItems': 4,
'minItems': 2,
'type': 'array'},
'compatible': {'oneOf': [{'additionalItems': False,
'items': [{'enum':
['mediatek,mt2701-smi-common',
'mediatek,mt2712-smi-common',
'mediatek,mt6779-smi-common',
'mediatek,mt8173-smi-common',
'mediatek,mt8183-smi-common',
'mediatek,mt8192-smi-common']}],
'maxItems': 1,
'minItems': 1,
'type': 'array'},
{'additionalItems': False,
'items': [{'const':
'mediatek,mt7623-smi-common'},
{'const':
'mediatek,mt2701-smi-common'}],
'maxItems': 2,
'minItems': 2,
'type': 'array'}]},
'phandle': True,
'pinctrl-names': True,
'power-domains': {'maxItems': 1, 'minItems': 1},
'reg': {'maxItems': 1, 'minItems': 1},
'status': True},
'required': ['compatible',
'reg',
'power-domains',
'clocks',
'clock-names'],
'select': {'properties': {'compatible': {'contains': {'enum':
['mediatek,mt2701-smi-common',
'mediatek,mt2712-smi-common',
'mediatek,mt6779-smi-common',
'mediatek,mt7623-smi-common',
'mediatek,mt8173-smi-common',
'mediatek,mt8183-smi-common',
'mediatek,mt8192-smi-common']}}},
'required': ['compatible']},
'title': 'SMI (Smart Multimedia Interface) Common'}
From
schema: .../Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
=================================
Sorry, I didn't find a example of multi "if-then" in oneOf and don't
know how to fix this.
From [1], "allOf" looks also is allowed... In this case, both allOf and
anyOf have no warning when dt_binding_check. only oneOf has the warning
log above.
Any suggestion is appreciated.
[1]
https://elixir.bootlin.com/linux/v5.9-rc1/source/Documentation/devicetree/bindings/example-schema.yaml#L195
>
> Best regards,
> Krzysztof
>
> > - if: #gen1 hw
> > then:
> > use apb/smi/async clocks
> >
> > - if: #gen2 hw that has gals.
> > then:
> > use apb/smi/gals0/gals1 clocks
> > else: # gen2 hw that doesn't have gals.
> > use apb/smi clocks.
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^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI to DT schema
2020-10-12 12:01 ` Yong Wu
@ 2020-10-12 13:26 ` Krzysztof Kozlowski
2020-10-13 7:53 ` Yong Wu
0 siblings, 1 reply; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-12 13:26 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Mon, 12 Oct 2020 at 14:02, Yong Wu <yong.wu@mediatek.com> wrote:
>
> On Mon, 2020-10-12 at 09:18 +0200, Krzysztof Kozlowski wrote:
> > On Sat, Oct 10, 2020 at 02:18:11PM +0800, Yong Wu wrote:
> > > On Tue, 2020-10-06 at 09:15 +0200, Krzysztof Kozlowski wrote:
> > > > On Tue, 6 Oct 2020 at 06:27, Yong Wu <yong.wu@mediatek.com> wrote:
> > > > >
> > > > > On Fri, 2020-10-02 at 13:08 +0200, Krzysztof Kozlowski wrote:
> > > > > > On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> > > > > > > Convert MediaTek SMI to DT schema.
> > > > > > >
> > > > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > > > > > ---
> > > > > > > .../mediatek,smi-common.txt | 49 ---------
> > > > > > > .../mediatek,smi-common.yaml | 100 ++++++++++++++++++
> > > > > > > .../memory-controllers/mediatek,smi-larb.txt | 49 ---------
> > > > > > > .../memory-controllers/mediatek,smi-larb.yaml | 91 ++++++++++++++++
> > > > > > > 4 files changed, 191 insertions(+), 98 deletions(-)
> > > > > > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> > > > > > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> > > > > > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> > > > > > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> > > > > ...
> > > > > > > +properties:
> > > > > > > + compatible:
> > > > > > > + oneOf:
> > > > > > > + - enum:
> > > > > > > + - mediatek,mt2701-smi-common
> > > > > > > + - mediatek,mt2712-smi-common
> > > > > > > + - mediatek,mt6779-smi-common
> > > > > > > + - mediatek,mt8173-smi-common
> > > > > > > + - mediatek,mt8183-smi-common
> > > > > > > +
> > > > > > > + - description: for mt7623
> > > > > > > + items:
> > > > > > > + - const: mediatek,mt7623-smi-common
> > > > > > > + - const: mediatek,mt2701-smi-common
> > > > > > > +
> > > > > > > + reg:
> > > > > > > + maxItems: 1
> > > > > > > +
> > > > > > > + clocks:
> > > > > > > + description: |
> > > > > > > + apb and smi are mandatory. the async is only for generation 1 smi HW.
> > > > > > > + gals(global async local sync) also is optional, here is the list which
> > > > > > > + require gals: mt6779 and mt8183.
> > > > > > > + minItems: 2
> > > > > > > + maxItems: 4
> > > > > > > + items:
> > > > > > > + - description: apb is Advanced Peripheral Bus clock, It's the clock for
> > > > > > > + setting the register.
> > > > > > > + - description: smi is the clock for transfer data and command.
> > > > > > > + - description: async is asynchronous clock, it help transform the smi clock
> > > > > > > + into the emi clock domain.
> > > > > > > + - description: gals0 is the path0 clock of gals.
> > > > > > > + - description: gals1 is the path1 clock of gals.
> > > > > > > +
> > > > > > > + clock-names:
> > > > > > > + oneOf:
> > > > > > > + - items:
> > > > > > > + - const: apb
> > > > > > > + - const: smi
> > > > > > > + - items:
> > > > > > > + - const: apb
> > > > > > > + - const: smi
> > > > > > > + - const: async
> > > > > > > + - items:
> > > > > > > + - const: apb
> > > > > > > + - const: smi
> > > > > > > + - const: gals0
> > > > > > > + - const: gals1
> > > > > >
> > > > > > Similarly to my comment to other properties, this requirement per
> > > > > > compatible should be part of the schema within 'if-then'.
> > > > >
> > > > > I'm not so familiar with this format. Do this has "if-then-'else
> > > > > if'-then-else"?
> > > >
> > > > These are mutually exclusive conditions, so you can skip else:
> > > > - if-then
> > > > - if-then
> > > > - if-then
> > > > It will be more readable then stacking 'if' under 'else'
> > >
> > > Thanks. I will use something like this:
> > >
> > > anyOf:
> >
> > Then it should be oneOf as only one condition can be valid.
>
> I did do this at the beginning. But I get a warning log when
> dt_binding_check.
Mhmm, right, since "if-else" matches in either of arms, then oneOf
will complain as it expects only one of items to match. Then just go
with allOf. anyOf might match zero of items, so it would not catch
actual errors, I think.
Best regards,
Krzysztof
_______________________________________________
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^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI to DT schema
2020-10-12 13:26 ` Krzysztof Kozlowski
@ 2020-10-13 7:53 ` Yong Wu
0 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-10-13 7:53 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Mon, 2020-10-12 at 15:26 +0200, Krzysztof Kozlowski wrote:
> On Mon, 12 Oct 2020 at 14:02, Yong Wu <yong.wu@mediatek.com> wrote:
> >
> > On Mon, 2020-10-12 at 09:18 +0200, Krzysztof Kozlowski wrote:
> > > On Sat, Oct 10, 2020 at 02:18:11PM +0800, Yong Wu wrote:
> > > > On Tue, 2020-10-06 at 09:15 +0200, Krzysztof Kozlowski wrote:
> > > > > On Tue, 6 Oct 2020 at 06:27, Yong Wu <yong.wu@mediatek.com> wrote:
> > > > > >
> > > > > > On Fri, 2020-10-02 at 13:08 +0200, Krzysztof Kozlowski wrote:
> > > > > > > On Wed, Sep 30, 2020 at 03:06:25PM +0800, Yong Wu wrote:
> > > > > > > > Convert MediaTek SMI to DT schema.
> > > > > > > >
> > > > > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > > > > > > ---
> > > > > > > > .../mediatek,smi-common.txt | 49 ---------
> > > > > > > > .../mediatek,smi-common.yaml | 100 ++++++++++++++++++
> > > > > > > > .../memory-controllers/mediatek,smi-larb.txt | 49 ---------
> > > > > > > > .../memory-controllers/mediatek,smi-larb.yaml | 91 ++++++++++++++++
> > > > > > > > 4 files changed, 191 insertions(+), 98 deletions(-)
> > > > > > > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
> > > > > > > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
> > > > > > > > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> > > > > > > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> > > > > > ...
> > > > > > > > +properties:
> > > > > > > > + compatible:
> > > > > > > > + oneOf:
> > > > > > > > + - enum:
> > > > > > > > + - mediatek,mt2701-smi-common
> > > > > > > > + - mediatek,mt2712-smi-common
> > > > > > > > + - mediatek,mt6779-smi-common
> > > > > > > > + - mediatek,mt8173-smi-common
> > > > > > > > + - mediatek,mt8183-smi-common
> > > > > > > > +
> > > > > > > > + - description: for mt7623
> > > > > > > > + items:
> > > > > > > > + - const: mediatek,mt7623-smi-common
> > > > > > > > + - const: mediatek,mt2701-smi-common
> > > > > > > > +
> > > > > > > > + reg:
> > > > > > > > + maxItems: 1
> > > > > > > > +
> > > > > > > > + clocks:
> > > > > > > > + description: |
> > > > > > > > + apb and smi are mandatory. the async is only for generation 1 smi HW.
> > > > > > > > + gals(global async local sync) also is optional, here is the list which
> > > > > > > > + require gals: mt6779 and mt8183.
> > > > > > > > + minItems: 2
> > > > > > > > + maxItems: 4
> > > > > > > > + items:
> > > > > > > > + - description: apb is Advanced Peripheral Bus clock, It's the clock for
> > > > > > > > + setting the register.
> > > > > > > > + - description: smi is the clock for transfer data and command.
> > > > > > > > + - description: async is asynchronous clock, it help transform the smi clock
> > > > > > > > + into the emi clock domain.
> > > > > > > > + - description: gals0 is the path0 clock of gals.
> > > > > > > > + - description: gals1 is the path1 clock of gals.
> > > > > > > > +
> > > > > > > > + clock-names:
> > > > > > > > + oneOf:
> > > > > > > > + - items:
> > > > > > > > + - const: apb
> > > > > > > > + - const: smi
> > > > > > > > + - items:
> > > > > > > > + - const: apb
> > > > > > > > + - const: smi
> > > > > > > > + - const: async
> > > > > > > > + - items:
> > > > > > > > + - const: apb
> > > > > > > > + - const: smi
> > > > > > > > + - const: gals0
> > > > > > > > + - const: gals1
> > > > > > >
> > > > > > > Similarly to my comment to other properties, this requirement per
> > > > > > > compatible should be part of the schema within 'if-then'.
> > > > > >
> > > > > > I'm not so familiar with this format. Do this has "if-then-'else
> > > > > > if'-then-else"?
> > > > >
> > > > > These are mutually exclusive conditions, so you can skip else:
> > > > > - if-then
> > > > > - if-then
> > > > > - if-then
> > > > > It will be more readable then stacking 'if' under 'else'
> > > >
> > > > Thanks. I will use something like this:
> > > >
> > > > anyOf:
> > >
> > > Then it should be oneOf as only one condition can be valid.
> >
> > I did do this at the beginning. But I get a warning log when
> > dt_binding_check.
>
> Mhmm, right, since "if-else" matches in either of arms, then oneOf
> will complain as it expects only one of items to match. Then just go
> with allOf. anyOf might match zero of items, so it would not catch
> actual errors, I think.
Thanks for the confirm. I will use "allOf" in next version.
>
> Best regards,
> Krzysztof
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^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v3 03/24] dt-bindings: memory: mediatek: Add a common larb-port header file
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
2020-09-30 7:06 ` [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Yong Wu
2020-09-30 7:06 ` [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI " Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 04/24] dt-bindings: memory: mediatek: Extend LARB_NR_MAX to 32 Yong Wu
` (21 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Put all the macros about smi larb/port togethers, this is a preparing
patch for extending LARB_NR and adding new dom-id support.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
include/dt-bindings/memory/mt2712-larb-port.h | 2 +-
include/dt-bindings/memory/mt6779-larb-port.h | 2 +-
include/dt-bindings/memory/mt8173-larb-port.h | 2 +-
include/dt-bindings/memory/mt8183-larb-port.h | 2 +-
include/dt-bindings/memory/mtk-smi-larb-port.h | 15 +++++++++++++++
5 files changed, 19 insertions(+), 4 deletions(-)
create mode 100644 include/dt-bindings/memory/mtk-smi-larb-port.h
diff --git a/include/dt-bindings/memory/mt2712-larb-port.h b/include/dt-bindings/memory/mt2712-larb-port.h
index 6f9aa7349cef..b6b2c6bf4459 100644
--- a/include/dt-bindings/memory/mt2712-larb-port.h
+++ b/include/dt-bindings/memory/mt2712-larb-port.h
@@ -6,7 +6,7 @@
#ifndef __DTS_IOMMU_PORT_MT2712_H
#define __DTS_IOMMU_PORT_MT2712_H
-#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+#include <dt-bindings/memory/mtk-smi-larb-port.h>
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h
index 2ad0899fbf2f..60f57f54393e 100644
--- a/include/dt-bindings/memory/mt6779-larb-port.h
+++ b/include/dt-bindings/memory/mt6779-larb-port.h
@@ -7,7 +7,7 @@
#ifndef _DTS_IOMMU_PORT_MT6779_H_
#define _DTS_IOMMU_PORT_MT6779_H_
-#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+#include <dt-bindings/memory/mtk-smi-larb-port.h>
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h
index 9f31ccfeca21..d8c99c946053 100644
--- a/include/dt-bindings/memory/mt8173-larb-port.h
+++ b/include/dt-bindings/memory/mt8173-larb-port.h
@@ -6,7 +6,7 @@
#ifndef __DTS_IOMMU_PORT_MT8173_H
#define __DTS_IOMMU_PORT_MT8173_H
-#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+#include <dt-bindings/memory/mtk-smi-larb-port.h>
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
diff --git a/include/dt-bindings/memory/mt8183-larb-port.h b/include/dt-bindings/memory/mt8183-larb-port.h
index 2c579f305162..275c095a6fd6 100644
--- a/include/dt-bindings/memory/mt8183-larb-port.h
+++ b/include/dt-bindings/memory/mt8183-larb-port.h
@@ -6,7 +6,7 @@
#ifndef __DTS_IOMMU_PORT_MT8183_H
#define __DTS_IOMMU_PORT_MT8183_H
-#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+#include <dt-bindings/memory/mtk-smi-larb-port.h>
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
diff --git a/include/dt-bindings/memory/mtk-smi-larb-port.h b/include/dt-bindings/memory/mtk-smi-larb-port.h
new file mode 100644
index 000000000000..2ec7fe5ce4e9
--- /dev/null
+++ b/include/dt-bindings/memory/mtk-smi-larb-port.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef __DTS_MTK_IOMMU_PORT_H_
+#define __DTS_MTK_IOMMU_PORT_H_
+
+#define MTK_LARB_NR_MAX 16
+
+#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf)
+#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
+
+#endif
--
2.18.0
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^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 04/24] dt-bindings: memory: mediatek: Extend LARB_NR_MAX to 32
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (2 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 03/24] dt-bindings: memory: mediatek: Add a common larb-port header file Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 05/24] dt-bindings: memory: mediatek: Add domain definition Yong Wu
` (20 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Extend the max larb number definition as mt8192 has larb_nr over 16.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../bindings/memory-controllers/mediatek,smi-larb.yaml | 2 +-
include/dt-bindings/memory/mtk-smi-larb-port.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
index 50793a0e6759..ea418113bf27 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -62,7 +62,7 @@ properties:
mediatek,larb-id:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
- maximum: 15
+ maximum: 31
description: the hardware id of this larb.
Required property for mt2701, mt2712, mt6779 and mt7623.
diff --git a/include/dt-bindings/memory/mtk-smi-larb-port.h b/include/dt-bindings/memory/mtk-smi-larb-port.h
index 2ec7fe5ce4e9..f4d8e3aed0bc 100644
--- a/include/dt-bindings/memory/mtk-smi-larb-port.h
+++ b/include/dt-bindings/memory/mtk-smi-larb-port.h
@@ -6,10 +6,10 @@
#ifndef __DTS_MTK_IOMMU_PORT_H_
#define __DTS_MTK_IOMMU_PORT_H_
-#define MTK_LARB_NR_MAX 16
+#define MTK_LARB_NR_MAX 32
#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
-#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf)
+#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f)
#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
#endif
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 05/24] dt-bindings: memory: mediatek: Add domain definition
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (3 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 04/24] dt-bindings: memory: mediatek: Extend LARB_NR_MAX to 32 Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU Yong Wu
` (19 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
In the latest SoC, there are several HW IP require a sepecial iova
range, mainly CCU and VPU has this requirement. Take CCU as a example,
CCU require its iova locate in the range(0x4000_0000 ~ 0x43ff_ffff).
In this patch we add a domain definition for the special port. In the
example of CCU, If we preassign CCU port in domain1, then iommu driver
will prepare a independent iommu domain of the special iova range for it,
then the iova got from dma_alloc_attrs(ccu-dev) will locate in its special
range.
This is a preparing patch for multi-domain support.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
include/dt-bindings/memory/mtk-smi-larb-port.h | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/memory/mtk-smi-larb-port.h b/include/dt-bindings/memory/mtk-smi-larb-port.h
index f4d8e3aed0bc..d00f5de8438b 100644
--- a/include/dt-bindings/memory/mtk-smi-larb-port.h
+++ b/include/dt-bindings/memory/mtk-smi-larb-port.h
@@ -7,9 +7,16 @@
#define __DTS_MTK_IOMMU_PORT_H_
#define MTK_LARB_NR_MAX 32
+#define MTK_M4U_DOM_NR_MAX 8
+
+#define MTK_M4U_DOM_ID(domid, larb, port) \
+ (((domid) & 0x7) << 16 | (((larb) & 0x1f) << 5) | ((port) & 0x1f))
+
+/* The default dom id is 0. */
+#define MTK_M4U_ID(larb, port) MTK_M4U_DOM_ID(0, larb, port)
-#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f)
#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
+#define MTK_M4U_TO_DOM(id) (((id) >> 16) & 0x7)
#endif
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (4 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 05/24] dt-bindings: memory: mediatek: Add domain definition Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-10-02 11:10 ` Krzysztof Kozlowski
2020-09-30 7:06 ` [PATCH v3 07/24] iommu/mediatek: Use the common mtk-smi-larb-port.h Yong Wu
` (18 subsequent siblings)
24 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
This patch adds decriptions for mt8192 IOMMU and SMI.
mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
table format. The M4U-SMI HW diagram is as below:
EMI
|
M4U
|
------------
SMI Common
------------
|
+-------+------+------+----------------------+-------+
| | | | ...... | |
| | | | | |
larb0 larb1 larb2 larb4 ...... larb19 larb20
disp0 disp1 mdp vdec IPE IPE
All the connections are HW fixed, SW can NOT adjust it.
mt8192 M4U support 0~16GB iova range. we preassign different engines
into different iova ranges:
domain-id module iova-range larbs
0 disp 0 ~ 4G larb0/1
1 vcodec 4G ~ 8G larb4/5/7
2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10
4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5
The iova range for CCU0/1(camera control unit) is HW requirement.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/iommu/mediatek,iommu.yaml | 9 +-
.../mediatek,smi-common.yaml | 5 +-
.../memory-controllers/mediatek,smi-larb.yaml | 3 +-
include/dt-bindings/memory/mt8192-larb-port.h | 239 ++++++++++++++++++
4 files changed, 251 insertions(+), 5 deletions(-)
create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index eae773ad53a3..a7f41cdf3aca 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -75,6 +75,7 @@ properties:
- mediatek,mt6779-m4u # mt6779 generation two HW
- mediatek,mt8173-m4u # mt8173 generation two HW
- mediatek,mt8183-m4u # mt8183 generation two HW
+ - mediatek,mt8192-m4u # mt8192 generation two HW
- description: mt7623 generation one HW
items:
@@ -90,7 +91,7 @@ properties:
clocks:
description: |
bclk is optional. here is the list which require this bclk:
- mt2701, mt2712, mt7623 and mt8173.
+ mt2701, mt2712, mt7623, mt8173 and mt8192.
M4U will use the EMI clock which always has been enabled before
kernel if there is no this bclk.
items:
@@ -116,7 +117,11 @@ properties:
dt-binding/memory/mt2712-larb-port.h for mt2712,
dt-binding/memory/mt6779-larb-port.h for mt6779,
dt-binding/memory/mt8173-larb-port.h for mt8173,
- dt-binding/memory/mt8183-larb-port.h for mt8183.
+ dt-binding/memory/mt8183-larb-port.h for mt8183,
+ dt-binding/memory/mt8192-larb-port.h for mt8192.
+
+ power-domains:
+ maxItems: 1
required:
- compatible
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
index 76ecc7205438..d3cb4d853e71 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -15,7 +15,7 @@ description: |+
MediaTek SMI have two generations of HW architecture, here is the list
which generation the SoCs use:
generation 1: mt2701 and mt7623.
- generation 2: mt2712, mt6779, mt8173 and mt8183.
+ generation 2: mt2712, mt6779, mt8173, mt8183 and mt8192.
There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
@@ -33,6 +33,7 @@ properties:
- mediatek,mt6779-smi-common
- mediatek,mt8173-smi-common
- mediatek,mt8183-smi-common
+ - mediatek,mt8192-smi-common
- description: for mt7623
items:
@@ -46,7 +47,7 @@ properties:
description: |
apb and smi are mandatory. the async is only for generation 1 smi HW.
gals(global async local sync) also is optional, here is the list which
- require gals: mt6779 and mt8183.
+ require gals: mt6779, mt8183 and mt8192.
minItems: 2
maxItems: 4
items:
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
index ea418113bf27..f5ba43638c37 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -21,6 +21,7 @@ properties:
- mediatek,mt6779-smi-larb
- mediatek,mt8173-smi-larb
- mediatek,mt8183-smi-larb
+ - mediatek,mt8192-smi-larb
- description: for mt7623
items:
@@ -64,7 +65,7 @@ properties:
minimum: 0
maximum: 31
description: the hardware id of this larb.
- Required property for mt2701, mt2712, mt6779 and mt7623.
+ Required property for mt2701, mt2712, mt6779, mt7623 and mt8192.
required:
- compatible
diff --git a/include/dt-bindings/memory/mt8192-larb-port.h b/include/dt-bindings/memory/mt8192-larb-port.h
new file mode 100644
index 000000000000..41c253662e90
--- /dev/null
+++ b/include/dt-bindings/memory/mt8192-larb-port.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Chao Hao <chao.hao@mediatek.com>
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef _DTS_IOMMU_PORT_MT8192_H_
+#define _DTS_IOMMU_PORT_MT8192_H_
+
+#include <dt-bindings/memory/mtk-smi-larb-port.h>
+
+/*
+ * MM IOMMU:
+ * domain 0: display: larb0, larb1.
+ * domain 1: vcodec: larb4, larb5, larb7.
+ * domain 2: CAM/MDP: larb2, larb9, larb11, larb13, larb14, larb16,
+ * larb17, larb18, larb19, larb20,
+ * domain 3: CCU0: larb13 - port9/10.
+ * domain 4: CCU1: larb14 - port4/5.
+ *
+ * larb3/6/8/10/12/15 is null.
+ */
+
+/* larb0 */
+#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_DOM_ID(0, 0, 0)
+#define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_DOM_ID(0, 0, 1)
+#define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_DOM_ID(0, 0, 2)
+#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_DOM_ID(0, 0, 3)
+#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_DOM_ID(0, 0, 4)
+#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_DOM_ID(0, 0, 5)
+
+/* larb1 */
+#define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_DOM_ID(0, 1, 0)
+#define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_DOM_ID(0, 1, 1)
+#define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_DOM_ID(0, 1, 2)
+#define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_DOM_ID(0, 1, 3)
+#define M4U_PORT_L1_DISP_MDP_RDMA4 MTK_M4U_DOM_ID(0, 1, 4)
+#define M4U_PORT_L1_DISP_RDMA4 MTK_M4U_DOM_ID(0, 1, 5)
+#define M4U_PORT_L1_DISP_UFBC_WDMA0 MTK_M4U_DOM_ID(0, 1, 6)
+#define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_DOM_ID(0, 1, 7)
+
+/* larb2 */
+#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_DOM_ID(2, 2, 0)
+#define M4U_PORT_L2_MDP_RDMA1 MTK_M4U_DOM_ID(2, 2, 1)
+#define M4U_PORT_L2_MDP_WROT0 MTK_M4U_DOM_ID(2, 2, 2)
+#define M4U_PORT_L2_MDP_WROT1 MTK_M4U_DOM_ID(2, 2, 3)
+#define M4U_PORT_L2_MDP_DISP_FAKE0 MTK_M4U_DOM_ID(2, 2, 4)
+
+/* larb3: null */
+
+/* larb4 */
+#define M4U_PORT_L4_VDEC_MC_EXT MTK_M4U_DOM_ID(1, 4, 0)
+#define M4U_PORT_L4_VDEC_UFO_EXT MTK_M4U_DOM_ID(1, 4, 1)
+#define M4U_PORT_L4_VDEC_PP_EXT MTK_M4U_DOM_ID(1, 4, 2)
+#define M4U_PORT_L4_VDEC_PRED_RD_EXT MTK_M4U_DOM_ID(1, 4, 3)
+#define M4U_PORT_L4_VDEC_PRED_WR_EXT MTK_M4U_DOM_ID(1, 4, 4)
+#define M4U_PORT_L4_VDEC_PPWRAP_EXT MTK_M4U_DOM_ID(1, 4, 5)
+#define M4U_PORT_L4_VDEC_TILE_EXT MTK_M4U_DOM_ID(1, 4, 6)
+#define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_DOM_ID(1, 4, 7)
+#define M4U_PORT_L4_VDEC_VLD2_EXT MTK_M4U_DOM_ID(1, 4, 8)
+#define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_DOM_ID(1, 4, 9)
+#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT MTK_M4U_DOM_ID(1, 4, 10)
+
+/* larb5 */
+#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT MTK_M4U_DOM_ID(1, 5, 0)
+#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT MTK_M4U_DOM_ID(1, 5, 1)
+#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT MTK_M4U_DOM_ID(1, 5, 2)
+#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT MTK_M4U_DOM_ID(1, 5, 3)
+#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT MTK_M4U_DOM_ID(1, 5, 4)
+#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT MTK_M4U_DOM_ID(1, 5, 5)
+#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT MTK_M4U_DOM_ID(1, 5, 6)
+#define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_DOM_ID(1, 5, 7)
+
+/* larb6: null */
+
+/* larb7 */
+#define M4U_PORT_L7_VENC_RCPU MTK_M4U_DOM_ID(1, 7, 0)
+#define M4U_PORT_L7_VENC_REC MTK_M4U_DOM_ID(1, 7, 1)
+#define M4U_PORT_L7_VENC_BSDMA MTK_M4U_DOM_ID(1, 7, 2)
+#define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_DOM_ID(1, 7, 3)
+#define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_DOM_ID(1, 7, 4)
+#define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_DOM_ID(1, 7, 5)
+#define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_DOM_ID(1, 7, 6)
+#define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_DOM_ID(1, 7, 7)
+#define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_DOM_ID(1, 7, 8)
+#define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_DOM_ID(1, 7, 9)
+#define M4U_PORT_L7_JPGENC_Q_RDMA MTK_M4U_DOM_ID(1, 7, 10)
+#define M4U_PORT_L7_JPGENC_C_TABLE MTK_M4U_DOM_ID(1, 7, 11)
+#define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_DOM_ID(1, 7, 12)
+#define M4U_PORT_L7_VENC_SUB_R_LUMA MTK_M4U_DOM_ID(1, 7, 13)
+#define M4U_PORT_L7_VENC_SUB_W_LUMA MTK_M4U_DOM_ID(1, 7, 14)
+
+/* larb8: null */
+
+/* larb9 */
+#define M4U_PORT_L9_IMG_IMGI_D1 MTK_M4U_DOM_ID(2, 9, 0)
+#define M4U_PORT_L9_IMG_IMGBI_D1 MTK_M4U_DOM_ID(2, 9, 1)
+#define M4U_PORT_L9_IMG_DMGI_D1 MTK_M4U_DOM_ID(2, 9, 2)
+#define M4U_PORT_L9_IMG_DEPI_D1 MTK_M4U_DOM_ID(2, 9, 3)
+#define M4U_PORT_L9_IMG_ICE_D1 MTK_M4U_DOM_ID(2, 9, 4)
+#define M4U_PORT_L9_IMG_SMTI_D1 MTK_M4U_DOM_ID(2, 9, 5)
+#define M4U_PORT_L9_IMG_SMTO_D2 MTK_M4U_DOM_ID(2, 9, 6)
+#define M4U_PORT_L9_IMG_SMTO_D1 MTK_M4U_DOM_ID(2, 9, 7)
+#define M4U_PORT_L9_IMG_CRZO_D1 MTK_M4U_DOM_ID(2, 9, 8)
+#define M4U_PORT_L9_IMG_IMG3O_D1 MTK_M4U_DOM_ID(2, 9, 9)
+#define M4U_PORT_L9_IMG_VIPI_D1 MTK_M4U_DOM_ID(2, 9, 10)
+#define M4U_PORT_L9_IMG_SMTI_D5 MTK_M4U_DOM_ID(2, 9, 11)
+#define M4U_PORT_L9_IMG_TIMGO_D1 MTK_M4U_DOM_ID(2, 9, 12)
+#define M4U_PORT_L9_IMG_UFBC_W0 MTK_M4U_DOM_ID(2, 9, 13)
+#define M4U_PORT_L9_IMG_UFBC_R0 MTK_M4U_DOM_ID(2, 9, 14)
+
+/* larb10: null */
+
+/* larb11 */
+#define M4U_PORT_L11_IMG_IMGI_D1 MTK_M4U_DOM_ID(2, 11, 0)
+#define M4U_PORT_L11_IMG_IMGBI_D1 MTK_M4U_DOM_ID(2, 11, 1)
+#define M4U_PORT_L11_IMG_DMGI_D1 MTK_M4U_DOM_ID(2, 11, 2)
+#define M4U_PORT_L11_IMG_DEPI_D1 MTK_M4U_DOM_ID(2, 11, 3)
+#define M4U_PORT_L11_IMG_ICE_D1 MTK_M4U_DOM_ID(2, 11, 4)
+#define M4U_PORT_L11_IMG_SMTI_D1 MTK_M4U_DOM_ID(2, 11, 5)
+#define M4U_PORT_L11_IMG_SMTO_D2 MTK_M4U_DOM_ID(2, 11, 6)
+#define M4U_PORT_L11_IMG_SMTO_D1 MTK_M4U_DOM_ID(2, 11, 7)
+#define M4U_PORT_L11_IMG_CRZO_D1 MTK_M4U_DOM_ID(2, 11, 8)
+#define M4U_PORT_L11_IMG_IMG3O_D1 MTK_M4U_DOM_ID(2, 11, 9)
+#define M4U_PORT_L11_IMG_VIPI_D1 MTK_M4U_DOM_ID(2, 11, 10)
+#define M4U_PORT_L11_IMG_SMTI_D5 MTK_M4U_DOM_ID(2, 11, 11)
+#define M4U_PORT_L11_IMG_TIMGO_D1 MTK_M4U_DOM_ID(2, 11, 12)
+#define M4U_PORT_L11_IMG_UFBC_W0 MTK_M4U_DOM_ID(2, 11, 13)
+#define M4U_PORT_L11_IMG_UFBC_R0 MTK_M4U_DOM_ID(2, 11, 14)
+#define M4U_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_DOM_ID(2, 11, 15)
+#define M4U_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_DOM_ID(2, 11, 16)
+#define M4U_PORT_L11_IMG_WPE_WDMA MTK_M4U_DOM_ID(2, 11, 17)
+#define M4U_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_DOM_ID(2, 11, 18)
+#define M4U_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_DOM_ID(2, 11, 19)
+#define M4U_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_DOM_ID(2, 11, 20)
+#define M4U_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_DOM_ID(2, 11, 21)
+#define M4U_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_DOM_ID(2, 11, 22)
+#define M4U_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_DOM_ID(2, 11, 23)
+#define M4U_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_DOM_ID(2, 11, 24)
+#define M4U_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_DOM_ID(2, 11, 25)
+
+/* larb12: null */
+
+/* larb13 */
+#define M4U_PORT_L13_CAM_MRAWI MTK_M4U_DOM_ID(2, 13, 0)
+#define M4U_PORT_L13_CAM_MRAWO0 MTK_M4U_DOM_ID(2, 13, 1)
+#define M4U_PORT_L13_CAM_MRAWO1 MTK_M4U_DOM_ID(2, 13, 2)
+#define M4U_PORT_L13_CAM_CAMSV1 MTK_M4U_DOM_ID(2, 13, 3)
+#define M4U_PORT_L13_CAM_CAMSV2 MTK_M4U_DOM_ID(2, 13, 4)
+#define M4U_PORT_L13_CAM_CAMSV3 MTK_M4U_DOM_ID(2, 13, 5)
+#define M4U_PORT_L13_CAM_CAMSV4 MTK_M4U_DOM_ID(2, 13, 6)
+#define M4U_PORT_L13_CAM_CAMSV5 MTK_M4U_DOM_ID(2, 13, 7)
+#define M4U_PORT_L13_CAM_CAMSV6 MTK_M4U_DOM_ID(2, 13, 8)
+#define M4U_PORT_L13_CAM_CCUI MTK_M4U_DOM_ID(3, 13, 9)
+#define M4U_PORT_L13_CAM_CCUO MTK_M4U_DOM_ID(3, 13, 10)
+#define M4U_PORT_L13_CAM_FAKE MTK_M4U_DOM_ID(2, 13, 11)
+
+/* larb14 */
+#define M4U_PORT_L14_CAM_RESERVE1 MTK_M4U_DOM_ID(2, 14, 0)
+#define M4U_PORT_L14_CAM_RESERVE2 MTK_M4U_DOM_ID(2, 14, 1)
+#define M4U_PORT_L14_CAM_RESERVE3 MTK_M4U_DOM_ID(2, 14, 2)
+#define M4U_PORT_L14_CAM_CAMSV0 MTK_M4U_DOM_ID(2, 14, 3)
+#define M4U_PORT_L14_CAM_CCUI MTK_M4U_DOM_ID(4, 14, 4)
+#define M4U_PORT_L14_CAM_CCUO MTK_M4U_DOM_ID(4, 14, 5)
+
+/* larb15: null */
+
+/* larb16 */
+#define M4U_PORT_L16_CAM_IMGO_R1_A MTK_M4U_DOM_ID(2, 16, 0)
+#define M4U_PORT_L16_CAM_RRZO_R1_A MTK_M4U_DOM_ID(2, 16, 1)
+#define M4U_PORT_L16_CAM_CQI_R1_A MTK_M4U_DOM_ID(2, 16, 2)
+#define M4U_PORT_L16_CAM_BPCI_R1_A MTK_M4U_DOM_ID(2, 16, 3)
+#define M4U_PORT_L16_CAM_YUVO_R1_A MTK_M4U_DOM_ID(2, 16, 4)
+#define M4U_PORT_L16_CAM_UFDI_R2_A MTK_M4U_DOM_ID(2, 16, 5)
+#define M4U_PORT_L16_CAM_RAWI_R2_A MTK_M4U_DOM_ID(2, 16, 6)
+#define M4U_PORT_L16_CAM_RAWI_R3_A MTK_M4U_DOM_ID(2, 16, 7)
+#define M4U_PORT_L16_CAM_AAO_R1_A MTK_M4U_DOM_ID(2, 16, 8)
+#define M4U_PORT_L16_CAM_AFO_R1_A MTK_M4U_DOM_ID(2, 16, 9)
+#define M4U_PORT_L16_CAM_FLKO_R1_A MTK_M4U_DOM_ID(2, 16, 10)
+#define M4U_PORT_L16_CAM_LCESO_R1_A MTK_M4U_DOM_ID(2, 16, 11)
+#define M4U_PORT_L16_CAM_CRZO_R1_A MTK_M4U_DOM_ID(2, 16, 12)
+#define M4U_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_DOM_ID(2, 16, 13)
+#define M4U_PORT_L16_CAM_RSSO_R1_A MTK_M4U_DOM_ID(2, 16, 14)
+#define M4U_PORT_L16_CAM_AAHO_R1_A MTK_M4U_DOM_ID(2, 16, 15)
+#define M4U_PORT_L16_CAM_LSCI_R1_A MTK_M4U_DOM_ID(2, 16, 16)
+
+/* larb17 */
+#define M4U_PORT_L17_CAM_IMGO_R1_B MTK_M4U_DOM_ID(2, 17, 0)
+#define M4U_PORT_L17_CAM_RRZO_R1_B MTK_M4U_DOM_ID(2, 17, 1)
+#define M4U_PORT_L17_CAM_CQI_R1_B MTK_M4U_DOM_ID(2, 17, 2)
+#define M4U_PORT_L17_CAM_BPCI_R1_B MTK_M4U_DOM_ID(2, 17, 3)
+#define M4U_PORT_L17_CAM_YUVO_R1_B MTK_M4U_DOM_ID(2, 17, 4)
+#define M4U_PORT_L17_CAM_UFDI_R2_B MTK_M4U_DOM_ID(2, 17, 5)
+#define M4U_PORT_L17_CAM_RAWI_R2_B MTK_M4U_DOM_ID(2, 17, 6)
+#define M4U_PORT_L17_CAM_RAWI_R3_B MTK_M4U_DOM_ID(2, 17, 7)
+#define M4U_PORT_L17_CAM_AAO_R1_B MTK_M4U_DOM_ID(2, 17, 8)
+#define M4U_PORT_L17_CAM_AFO_R1_B MTK_M4U_DOM_ID(2, 17, 9)
+#define M4U_PORT_L17_CAM_FLKO_R1_B MTK_M4U_DOM_ID(2, 17, 10)
+#define M4U_PORT_L17_CAM_LCESO_R1_B MTK_M4U_DOM_ID(2, 17, 11)
+#define M4U_PORT_L17_CAM_CRZO_R1_B MTK_M4U_DOM_ID(2, 17, 12)
+#define M4U_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_DOM_ID(2, 17, 13)
+#define M4U_PORT_L17_CAM_RSSO_R1_B MTK_M4U_DOM_ID(2, 17, 14)
+#define M4U_PORT_L17_CAM_AAHO_R1_B MTK_M4U_DOM_ID(2, 17, 15)
+#define M4U_PORT_L17_CAM_LSCI_R1_B MTK_M4U_DOM_ID(2, 17, 16)
+
+/* larb18 */
+#define M4U_PORT_L18_CAM_IMGO_R1_C MTK_M4U_DOM_ID(2, 18, 0)
+#define M4U_PORT_L18_CAM_RRZO_R1_C MTK_M4U_DOM_ID(2, 18, 1)
+#define M4U_PORT_L18_CAM_CQI_R1_C MTK_M4U_DOM_ID(2, 18, 2)
+#define M4U_PORT_L18_CAM_BPCI_R1_C MTK_M4U_DOM_ID(2, 18, 3)
+#define M4U_PORT_L18_CAM_YUVO_R1_C MTK_M4U_DOM_ID(2, 18, 4)
+#define M4U_PORT_L18_CAM_UFDI_R2_C MTK_M4U_DOM_ID(2, 18, 5)
+#define M4U_PORT_L18_CAM_RAWI_R2_C MTK_M4U_DOM_ID(2, 18, 6)
+#define M4U_PORT_L18_CAM_RAWI_R3_C MTK_M4U_DOM_ID(2, 18, 7)
+#define M4U_PORT_L18_CAM_AAO_R1_C MTK_M4U_DOM_ID(2, 18, 8)
+#define M4U_PORT_L18_CAM_AFO_R1_C MTK_M4U_DOM_ID(2, 18, 9)
+#define M4U_PORT_L18_CAM_FLKO_R1_C MTK_M4U_DOM_ID(2, 18, 10)
+#define M4U_PORT_L18_CAM_LCESO_R1_C MTK_M4U_DOM_ID(2, 18, 11)
+#define M4U_PORT_L18_CAM_CRZO_R1_C MTK_M4U_DOM_ID(2, 18, 12)
+#define M4U_PORT_L18_CAM_LTMSO_R1_C MTK_M4U_DOM_ID(2, 18, 13)
+#define M4U_PORT_L18_CAM_RSSO_R1_C MTK_M4U_DOM_ID(2, 18, 14)
+#define M4U_PORT_L18_CAM_AAHO_R1_C MTK_M4U_DOM_ID(2, 18, 15)
+#define M4U_PORT_L18_CAM_LSCI_R1_C MTK_M4U_DOM_ID(2, 18, 16)
+
+/* larb19 */
+#define M4U_PORT_L19_IPE_DVS_RDMA MTK_M4U_DOM_ID(2, 19, 0)
+#define M4U_PORT_L19_IPE_DVS_WDMA MTK_M4U_DOM_ID(2, 19, 1)
+#define M4U_PORT_L19_IPE_DVP_RDMA MTK_M4U_DOM_ID(2, 19, 2)
+#define M4U_PORT_L19_IPE_DVP_WDMA MTK_M4U_DOM_ID(2, 19, 3)
+
+/* larb20 */
+#define M4U_PORT_L20_IPE_FDVT_RDA MTK_M4U_DOM_ID(2, 20, 0)
+#define M4U_PORT_L20_IPE_FDVT_RDB MTK_M4U_DOM_ID(2, 20, 1)
+#define M4U_PORT_L20_IPE_FDVT_WRA MTK_M4U_DOM_ID(2, 20, 2)
+#define M4U_PORT_L20_IPE_FDVT_WRB MTK_M4U_DOM_ID(2, 20, 3)
+#define M4U_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_DOM_ID(2, 20, 4)
+#define M4U_PORT_L20_IPE_RSC_WDMA MTK_M4U_DOM_ID(2, 20, 5)
+
+#endif
--
2.18.0
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^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU
2020-09-30 7:06 ` [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU Yong Wu
@ 2020-10-02 11:10 ` Krzysztof Kozlowski
2020-10-06 4:26 ` Yong Wu
0 siblings, 1 reply; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-02 11:10 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote:
> This patch adds decriptions for mt8192 IOMMU and SMI.
>
> mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> table format. The M4U-SMI HW diagram is as below:
>
> EMI
> |
> M4U
> |
> ------------
> SMI Common
> ------------
> |
> +-------+------+------+----------------------+-------+
> | | | | ...... | |
> | | | | | |
> larb0 larb1 larb2 larb4 ...... larb19 larb20
> disp0 disp1 mdp vdec IPE IPE
>
> All the connections are HW fixed, SW can NOT adjust it.
>
> mt8192 M4U support 0~16GB iova range. we preassign different engines
> into different iova ranges:
>
> domain-id module iova-range larbs
> 0 disp 0 ~ 4G larb0/1
> 1 vcodec 4G ~ 8G larb4/5/7
> 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
> 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10
> 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5
>
> The iova range for CCU0/1(camera control unit) is HW requirement.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/iommu/mediatek,iommu.yaml | 9 +-
> .../mediatek,smi-common.yaml | 5 +-
> .../memory-controllers/mediatek,smi-larb.yaml | 3 +-
> include/dt-bindings/memory/mt8192-larb-port.h | 239 ++++++++++++++++++
> 4 files changed, 251 insertions(+), 5 deletions(-)
> create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h
I see it depends on previous patches but does it have to be within one
commit? Is it not bisectable? The memory changes/bindings could go via
memory tree if this is split.
Best regards,
Krzysztof
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU
2020-10-02 11:10 ` Krzysztof Kozlowski
@ 2020-10-06 4:26 ` Yong Wu
2020-10-06 7:19 ` Krzysztof Kozlowski
0 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-10-06 4:26 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
Hi Krzysztof,
On Fri, 2020-10-02 at 13:10 +0200, Krzysztof Kozlowski wrote:
> On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote:
> > This patch adds decriptions for mt8192 IOMMU and SMI.
> >
> > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> > table format. The M4U-SMI HW diagram is as below:
> >
> > EMI
> > |
> > M4U
> > |
> > ------------
> > SMI Common
> > ------------
> > |
> > +-------+------+------+----------------------+-------+
> > | | | | ...... | |
> > | | | | | |
> > larb0 larb1 larb2 larb4 ...... larb19 larb20
> > disp0 disp1 mdp vdec IPE IPE
> >
> > All the connections are HW fixed, SW can NOT adjust it.
> >
> > mt8192 M4U support 0~16GB iova range. we preassign different engines
> > into different iova ranges:
> >
> > domain-id module iova-range larbs
> > 0 disp 0 ~ 4G larb0/1
> > 1 vcodec 4G ~ 8G larb4/5/7
> > 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
> > 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10
> > 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5
> >
> > The iova range for CCU0/1(camera control unit) is HW requirement.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > ---
> > .../bindings/iommu/mediatek,iommu.yaml | 9 +-
> > .../mediatek,smi-common.yaml | 5 +-
> > .../memory-controllers/mediatek,smi-larb.yaml | 3 +-
> > include/dt-bindings/memory/mt8192-larb-port.h | 239 ++++++++++++++++++
> > 4 files changed, 251 insertions(+), 5 deletions(-)
> > create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h
>
> I see it depends on previous patches but does it have to be within one
> commit? Is it not bisectable? The memory changes/bindings could go via
> memory tree if this is split.
Thanks for the view.
I can split this into two patchset in next version, one is for iommu and
the other is for smi.
Only the patch [18/24] change both the code(iommu and smi). I don't plan
to split it, and the smi patch[24/24] don't depend on it(won't
conflict).
since 18/24 also touch the smi code, I expect it could get Acked-by from
you or Matthias, then Joerg could take it.
Thanks.
>
> Best regards,
> Krzysztof
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU
2020-10-06 4:26 ` Yong Wu
@ 2020-10-06 7:19 ` Krzysztof Kozlowski
0 siblings, 0 replies; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-06 7:19 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Tue, Oct 06, 2020 at 12:26:45PM +0800, Yong Wu wrote:
> Hi Krzysztof,
>
> On Fri, 2020-10-02 at 13:10 +0200, Krzysztof Kozlowski wrote:
> > On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote:
> > > This patch adds decriptions for mt8192 IOMMU and SMI.
> > >
> > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> > > table format. The M4U-SMI HW diagram is as below:
> > >
> > > EMI
> > > |
> > > M4U
> > > |
> > > ------------
> > > SMI Common
> > > ------------
> > > |
> > > +-------+------+------+----------------------+-------+
> > > | | | | ...... | |
> > > | | | | | |
> > > larb0 larb1 larb2 larb4 ...... larb19 larb20
> > > disp0 disp1 mdp vdec IPE IPE
> > >
> > > All the connections are HW fixed, SW can NOT adjust it.
> > >
> > > mt8192 M4U support 0~16GB iova range. we preassign different engines
> > > into different iova ranges:
> > >
> > > domain-id module iova-range larbs
> > > 0 disp 0 ~ 4G larb0/1
> > > 1 vcodec 4G ~ 8G larb4/5/7
> > > 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
> > > 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10
> > > 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5
> > >
> > > The iova range for CCU0/1(camera control unit) is HW requirement.
> > >
> > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > ---
> > > .../bindings/iommu/mediatek,iommu.yaml | 9 +-
> > > .../mediatek,smi-common.yaml | 5 +-
> > > .../memory-controllers/mediatek,smi-larb.yaml | 3 +-
> > > include/dt-bindings/memory/mt8192-larb-port.h | 239 ++++++++++++++++++
> > > 4 files changed, 251 insertions(+), 5 deletions(-)
> > > create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h
> >
> > I see it depends on previous patches but does it have to be within one
> > commit? Is it not bisectable? The memory changes/bindings could go via
> > memory tree if this is split.
>
> Thanks for the view.
>
> I can split this into two patchset in next version, one is for iommu and
> the other is for smi.
>
> Only the patch [18/24] change both the code(iommu and smi). I don't plan
> to split it, and the smi patch[24/24] don't depend on it(won't
> conflict).
It got too late in the cycle, so I am not going to take the 24/24 now.
>
> since 18/24 also touch the smi code, I expect it could get Acked-by from
> you or Matthias, then Joerg could take it.
Sure. I acked it.
Best regards,
Krzysztof
_______________________________________________
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iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v3 07/24] iommu/mediatek: Use the common mtk-smi-larb-port.h
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (5 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 08/24] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap Yong Wu
` (17 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Use the common larb-port header in the source code.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 7 -------
drivers/iommu/mtk_iommu.h | 1 +
drivers/memory/mtk-smi.c | 1 +
include/soc/mediatek/smi.h | 2 --
4 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 785b228d39a6..fd8322ee4980 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -101,13 +101,6 @@
#define MTK_PROTECT_PA_ALIGN 256
-/*
- * Get the local arbiter ID and the portid within the larb arbiter
- * from mtk_m4u_id which is defined by MTK_M4U_ID.
- */
-#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf)
-#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
-
#define HAS_4GB_MODE BIT(0)
/* HW will use the EMI clock if there isn't the "bclk". */
#define HAS_BCLK BIT(1)
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 122925dbe547..a2e2c844b96e 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -17,6 +17,7 @@
#include <linux/spinlock.h>
#include <linux/dma-mapping.h>
#include <soc/mediatek/smi.h>
+#include <dt-bindings/memory/mtk-smi-larb-port.h>
#define MTK_LARB_COM_MAX 8
#define MTK_LARB_SUBCOM_MAX 4
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index c21262502581..ec83f1ac48b1 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -14,6 +14,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <soc/mediatek/smi.h>
+#include <dt-bindings/memory/mtk-smi-larb-port.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
/* mt8173 */
diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
index 5a34b87d89e3..9371bf572ab8 100644
--- a/include/soc/mediatek/smi.h
+++ b/include/soc/mediatek/smi.h
@@ -11,8 +11,6 @@
#ifdef CONFIG_MTK_SMI
-#define MTK_LARB_NR_MAX 16
-
#define MTK_SMI_MMU_EN(port) BIT(port)
struct mtk_smi_larb_iommu {
--
2.18.0
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^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 08/24] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (6 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 07/24] iommu/mediatek: Use the common mtk-smi-larb-port.h Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-10-23 11:17 ` Will Deacon
2020-09-30 7:06 ` [PATCH v3 09/24] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Yong Wu
` (16 subsequent siblings)
24 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Use the ias for the valid iova checking in arm_v7s_unmap. This is a
preparing patch for supporting iova 34bit for MediaTek.
BTW, change the ias/oas checking format in arm_v7s_map.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index a688f22cbe3b..4c9d8dccfc5a 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -526,8 +526,7 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
return 0;
- if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
- paddr >= (1ULL << data->iop.cfg.oas)))
+ if (WARN_ON(iova >> data->iop.cfg.ias || paddr >> data->iop.cfg.oas))
return -ERANGE;
ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd, gfp);
@@ -717,7 +716,7 @@ static size_t arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova,
{
struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
- if (WARN_ON(upper_32_bits(iova)))
+ if (WARN_ON(iova >> data->iop.cfg.ias))
return 0;
return __arm_v7s_unmap(data, gather, iova, size, 1, data->pgd);
--
2.18.0
_______________________________________________
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iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v3 08/24] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap
2020-09-30 7:06 ` [PATCH v3 08/24] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap Yong Wu
@ 2020-10-23 11:17 ` Will Deacon
2020-10-26 7:49 ` Yong Wu
0 siblings, 1 reply; 55+ messages in thread
From: Will Deacon @ 2020-10-23 11:17 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, Greg Kroah-Hartman, linux-kernel,
Evan Green, Tomasz Figa, iommu, Rob Herring, linux-mediatek,
Krzysztof Kozlowski, Matthias Brugger, ming-fan.chen, anan.sun,
Robin Murphy, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:31PM +0800, Yong Wu wrote:
> Use the ias for the valid iova checking in arm_v7s_unmap. This is a
> preparing patch for supporting iova 34bit for MediaTek.
> BTW, change the ias/oas checking format in arm_v7s_map.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index a688f22cbe3b..4c9d8dccfc5a 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -526,8 +526,7 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
> if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
> return 0;
>
> - if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
> - paddr >= (1ULL << data->iop.cfg.oas)))
> + if (WARN_ON(iova >> data->iop.cfg.ias || paddr >> data->iop.cfg.oas))
> return -ERANGE;
As discussed when reviewing these for Android, please leave this code as-is.
>
> ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd, gfp);
> @@ -717,7 +716,7 @@ static size_t arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova,
> {
> struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
>
> - if (WARN_ON(upper_32_bits(iova)))
> + if (WARN_ON(iova >> data->iop.cfg.ias))
> return 0;
And avoid the UB here for 32-bit machines by comparing with 1ULL <<
iop.cfg.ias instead.
Thanks,
Will
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v3 08/24] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap
2020-10-23 11:17 ` Will Deacon
@ 2020-10-26 7:49 ` Yong Wu
0 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-10-26 7:49 UTC (permalink / raw)
To: Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, Greg Kroah-Hartman, linux-kernel,
Evan Green, Tomasz Figa, iommu, Rob Herring, linux-mediatek,
Krzysztof Kozlowski, Matthias Brugger, ming-fan.chen, anan.sun,
Robin Murphy, linux-arm-kernel
On Fri, 2020-10-23 at 12:17 +0100, Will Deacon wrote:
> On Wed, Sep 30, 2020 at 03:06:31PM +0800, Yong Wu wrote:
> > Use the ias for the valid iova checking in arm_v7s_unmap. This is a
> > preparing patch for supporting iova 34bit for MediaTek.
> > BTW, change the ias/oas checking format in arm_v7s_map.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> > drivers/iommu/io-pgtable-arm-v7s.c | 5 ++---
> > 1 file changed, 2 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> > index a688f22cbe3b..4c9d8dccfc5a 100644
> > --- a/drivers/iommu/io-pgtable-arm-v7s.c
> > +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> > @@ -526,8 +526,7 @@ static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
> > if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
> > return 0;
> >
> > - if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
> > - paddr >= (1ULL << data->iop.cfg.oas)))
> > + if (WARN_ON(iova >> data->iop.cfg.ias || paddr >> data->iop.cfg.oas))
> > return -ERANGE;
>
> As discussed when reviewing these for Android, please leave this code as-is.
>
> >
> > ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd, gfp);
> > @@ -717,7 +716,7 @@ static size_t arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova,
> > {
> > struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
> >
> > - if (WARN_ON(upper_32_bits(iova)))
> > + if (WARN_ON(iova >> data->iop.cfg.ias))
> > return 0;
>
> And avoid the UB here for 32-bit machines by comparing with 1ULL <<
> iop.cfg.ias instead.
Thanks. I will fix it in next version.
>
> Thanks,
>
> Will
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v3 09/24] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (7 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 08/24] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-10-23 11:22 ` Will Deacon
2020-09-30 7:06 ` [PATCH v3 10/24] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros Yong Wu
` (15 subsequent siblings)
24 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 9 +++++++--
drivers/iommu/mtk_iommu.c | 2 +-
include/linux/io-pgtable.h | 4 ++--
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index 4c9d8dccfc5a..a3b3e9147b8d 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -112,9 +112,10 @@
#define ARM_V7S_TEX_MASK 0x7
#define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
-/* MediaTek extend the two bits for PA 32bit/33bit */
+/* MediaTek extend the bits below for PA 32bit/33bit/34bit */
#define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9)
#define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4)
+#define ARM_V7S_ATTR_MTK_PA_BIT34 BIT(5)
/* *well, except for TEX on level 2 large pages, of course :( */
#define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
@@ -194,6 +195,8 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
if (paddr & BIT_ULL(33))
pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
+ if (paddr & BIT_ULL(34))
+ pte |= ARM_V7S_ATTR_MTK_PA_BIT34;
return pte;
}
@@ -218,6 +221,8 @@ static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl,
paddr |= BIT_ULL(32);
if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
paddr |= BIT_ULL(33);
+ if (pte & ARM_V7S_ATTR_MTK_PA_BIT34)
+ paddr |= BIT_ULL(34);
return paddr;
}
@@ -753,7 +758,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
if (cfg->ias > ARM_V7S_ADDR_BITS)
return NULL;
- if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
+ if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
return NULL;
if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index fd8322ee4980..f6a2e3eb59d2 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -317,7 +317,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
IO_PGTABLE_QUIRK_ARM_MTK_EXT,
.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
.ias = 32,
- .oas = 34,
+ .oas = 35,
.tlb = &mtk_iommu_flush_ops,
.iommu_dev = data->dev,
};
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
index 23285ba645db..8c9a889d8df9 100644
--- a/include/linux/io-pgtable.h
+++ b/include/linux/io-pgtable.h
@@ -77,8 +77,8 @@ struct io_pgtable_cfg {
* TLB maintenance when mapping as well as when unmapping.
*
* IO_PGTABLE_QUIRK_ARM_MTK_EXT: (ARM v7s format) MediaTek IOMMUs extend
- * to support up to 34 bits PA where the bit32 and bit33 are
- * encoded in the bit9 and bit4 of the PTE respectively.
+ * to support up to 35 bits PA where the bit32, bit33 and bit34 are
+ * encoded in the bit9, bit4 and bit5 of the PTE respectively.
*
* IO_PGTABLE_QUIRK_NON_STRICT: Skip issuing synchronous leaf TLBIs
* on unmap, for DMA domains using the flush queue mechanism for
--
2.18.0
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iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v3 09/24] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek
2020-09-30 7:06 ` [PATCH v3 09/24] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Yong Wu
@ 2020-10-23 11:22 ` Will Deacon
0 siblings, 0 replies; 55+ messages in thread
From: Will Deacon @ 2020-10-23 11:22 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, Greg Kroah-Hartman, linux-kernel,
Evan Green, Tomasz Figa, iommu, Rob Herring, linux-mediatek,
Krzysztof Kozlowski, Matthias Brugger, ming-fan.chen, anan.sun,
Robin Murphy, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:32PM +0800, Yong Wu wrote:
> MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 9 +++++++--
> drivers/iommu/mtk_iommu.c | 2 +-
> include/linux/io-pgtable.h | 4 ++--
> 3 files changed, 10 insertions(+), 5 deletions(-)
Acked-by: Will Deacon <will@kernel.org>
Will
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v3 10/24] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (8 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 09/24] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-10-23 11:23 ` Will Deacon
2020-09-30 7:06 ` [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek Yong Wu
` (14 subsequent siblings)
24 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Add "cfg" as a parameter for some macros. This is a preparing patch for
mediatek extend the lvl1 pgtable. No functional change.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 34 +++++++++++++++---------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index a3b3e9147b8d..8362fdf76657 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -53,17 +53,17 @@
#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
#define ARM_V7S_TABLE_SHIFT 10
-#define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl))
-#define ARM_V7S_TABLE_SIZE(lvl) \
- (ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte))
+#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl))
+#define ARM_V7S_TABLE_SIZE(lvl, cfg) \
+ (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
#define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl))
#define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl)))
#define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT))
-#define _ARM_V7S_IDX_MASK(lvl) (ARM_V7S_PTES_PER_LVL(lvl) - 1)
-#define ARM_V7S_LVL_IDX(addr, lvl) ({ \
+#define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
+#define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \
int _l = lvl; \
- ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \
+ ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
})
/*
@@ -239,7 +239,7 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
struct device *dev = cfg->iommu_dev;
phys_addr_t phys;
dma_addr_t dma;
- size_t size = ARM_V7S_TABLE_SIZE(lvl);
+ size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
void *table = NULL;
if (lvl == 1)
@@ -285,7 +285,7 @@ static void __arm_v7s_free_table(void *table, int lvl,
{
struct io_pgtable_cfg *cfg = &data->iop.cfg;
struct device *dev = cfg->iommu_dev;
- size_t size = ARM_V7S_TABLE_SIZE(lvl);
+ size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
if (!cfg->coherent_walk)
dma_unmap_single(dev, __arm_v7s_dma_addr(table), size,
@@ -429,7 +429,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
arm_v7s_iopte *tblp;
size_t sz = ARM_V7S_BLOCK_SIZE(lvl);
- tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl);
+ tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl, cfg);
if (WARN_ON(__arm_v7s_unmap(data, NULL, iova + i * sz,
sz, lvl, tblp) != sz))
return -EINVAL;
@@ -482,7 +482,7 @@ static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova,
int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
/* Find our entry at the current level */
- ptep += ARM_V7S_LVL_IDX(iova, lvl);
+ ptep += ARM_V7S_LVL_IDX(iova, lvl, cfg);
/* If we can install a leaf entry at this level, then do so */
if (num_entries)
@@ -554,7 +554,7 @@ static void arm_v7s_free_pgtable(struct io_pgtable *iop)
struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop);
int i;
- for (i = 0; i < ARM_V7S_PTES_PER_LVL(1); i++) {
+ for (i = 0; i < ARM_V7S_PTES_PER_LVL(1, &data->iop.cfg); i++) {
arm_v7s_iopte pte = data->pgd[i];
if (ARM_V7S_PTE_IS_TABLE(pte, 1))
@@ -606,9 +606,9 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
if (!tablep)
return 0; /* Bytes unmapped */
- num_ptes = ARM_V7S_PTES_PER_LVL(2);
+ num_ptes = ARM_V7S_PTES_PER_LVL(2, cfg);
num_entries = size >> ARM_V7S_LVL_SHIFT(2);
- unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
+ unmap_idx = ARM_V7S_LVL_IDX(iova, 2, cfg);
pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
if (num_entries > 1)
@@ -650,7 +650,7 @@ static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
if (WARN_ON(lvl > 2))
return 0;
- idx = ARM_V7S_LVL_IDX(iova, lvl);
+ idx = ARM_V7S_LVL_IDX(iova, lvl, &iop->cfg);
ptep += idx;
do {
pte[i] = READ_ONCE(ptep[i]);
@@ -736,7 +736,7 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
u32 mask;
do {
- ptep += ARM_V7S_LVL_IDX(iova, ++lvl);
+ ptep += ARM_V7S_LVL_IDX(iova, ++lvl, &data->iop.cfg);
pte = READ_ONCE(*ptep);
ptep = iopte_deref(pte, lvl, data);
} while (ARM_V7S_PTE_IS_TABLE(pte, lvl));
@@ -779,8 +779,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
spin_lock_init(&data->split_lock);
data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
- ARM_V7S_TABLE_SIZE(2),
- ARM_V7S_TABLE_SIZE(2),
+ ARM_V7S_TABLE_SIZE(2, cfg),
+ ARM_V7S_TABLE_SIZE(2, cfg),
ARM_V7S_TABLE_SLAB_FLAGS, NULL);
if (!data->l2_tables)
goto out_free_data;
--
2.18.0
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^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v3 10/24] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros
2020-09-30 7:06 ` [PATCH v3 10/24] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros Yong Wu
@ 2020-10-23 11:23 ` Will Deacon
0 siblings, 0 replies; 55+ messages in thread
From: Will Deacon @ 2020-10-23 11:23 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, Greg Kroah-Hartman, linux-kernel,
Evan Green, Tomasz Figa, iommu, Rob Herring, linux-mediatek,
Krzysztof Kozlowski, Matthias Brugger, ming-fan.chen, anan.sun,
Robin Murphy, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:33PM +0800, Yong Wu wrote:
> Add "cfg" as a parameter for some macros. This is a preparing patch for
> mediatek extend the lvl1 pgtable. No functional change.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 34 +++++++++++++++---------------
> 1 file changed, 17 insertions(+), 17 deletions(-)
Acked-by: Will Deacon <will@kernel.org>
(but see my later comments above doing this for some of the 'constants' too)
Will
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^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (9 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 10/24] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-10-23 11:21 ` Will Deacon
2020-10-23 14:10 ` Robin Murphy
2020-09-30 7:06 ` [PATCH v3 12/24] iommu/mediatek: Move hw_init into attach_device Yong Wu
` (13 subsequent siblings)
24 siblings, 2 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
(4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
34bit.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++---
drivers/iommu/mtk_iommu.c | 2 +-
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index 8362fdf76657..306bae2755ed 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -50,10 +50,17 @@
*/
#define ARM_V7S_ADDR_BITS 32
#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
+/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
+#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6)
#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
#define ARM_V7S_TABLE_SHIFT 10
-#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl))
+#define ARM_V7S_PTES_PER_LVL(lvl, cfg) ({ \
+ int _lvl = lvl; \
+ !arm_v7s_is_mtk_enabled(cfg) ? \
+ (1 << _ARM_V7S_LVL_BITS(_lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(_lvl));\
+})
+
#define ARM_V7S_TABLE_SIZE(lvl, cfg) \
(ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
@@ -63,7 +70,7 @@
#define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
#define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \
int _l = lvl; \
- ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
+ ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
})
/*
@@ -755,7 +762,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
{
struct arm_v7s_io_pgtable *data;
- if (cfg->ias > ARM_V7S_ADDR_BITS)
+ if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
return NULL;
if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index f6a2e3eb59d2..6e85c9976a33 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
IO_PGTABLE_QUIRK_TLBI_ON_MAP |
IO_PGTABLE_QUIRK_ARM_MTK_EXT,
.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
- .ias = 32,
+ .ias = 34,
.oas = 35,
.tlb = &mtk_iommu_flush_ops,
.iommu_dev = data->dev,
--
2.18.0
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
2020-09-30 7:06 ` [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek Yong Wu
@ 2020-10-23 11:21 ` Will Deacon
2020-10-26 7:45 ` Yong Wu
2020-10-23 14:10 ` Robin Murphy
1 sibling, 1 reply; 55+ messages in thread
From: Will Deacon @ 2020-10-23 11:21 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, Greg Kroah-Hartman, linux-kernel,
Evan Green, Tomasz Figa, iommu, Rob Herring, linux-mediatek,
Krzysztof Kozlowski, Matthias Brugger, ming-fan.chen, anan.sun,
Robin Murphy, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:34PM +0800, Yong Wu wrote:
> The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> 34bit.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++---
> drivers/iommu/mtk_iommu.c | 2 +-
> 2 files changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index 8362fdf76657..306bae2755ed 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -50,10 +50,17 @@
> */
> #define ARM_V7S_ADDR_BITS 32
If we rename this to _ARM_V7S_ADDR_BITS can we then have ARM_V7S_ADDR_BITS
take a cfg parameter and move the arm_v7s_is_mtk_enabled() check in there?
Same for _ARM_V7S_LVL_BITS.
That would avoid scattering arm_v7s_is_mtk_enabled() into all the users.
Will
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^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
2020-10-23 11:21 ` Will Deacon
@ 2020-10-26 7:45 ` Yong Wu
0 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-10-26 7:45 UTC (permalink / raw)
To: Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, Greg Kroah-Hartman, linux-kernel,
Evan Green, Tomasz Figa, iommu, Rob Herring, linux-mediatek,
Krzysztof Kozlowski, Matthias Brugger, ming-fan.chen, anan.sun,
Robin Murphy, linux-arm-kernel
On Fri, 2020-10-23 at 12:21 +0100, Will Deacon wrote:
> On Wed, Sep 30, 2020 at 03:06:34PM +0800, Yong Wu wrote:
> > The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> > (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> > 34bit.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> > drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++---
> > drivers/iommu/mtk_iommu.c | 2 +-
> > 2 files changed, 11 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> > index 8362fdf76657..306bae2755ed 100644
> > --- a/drivers/iommu/io-pgtable-arm-v7s.c
> > +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> > @@ -50,10 +50,17 @@
> > */
> > #define ARM_V7S_ADDR_BITS 32
>
> If we rename this to _ARM_V7S_ADDR_BITS can we then have ARM_V7S_ADDR_BITS
> take a cfg parameter and move the arm_v7s_is_mtk_enabled() check in there?
> Same for _ARM_V7S_LVL_BITS.
>
> That would avoid scattering arm_v7s_is_mtk_enabled() into all the users.
I added "cfg" for _ARM_V7S_LVL_BITS in Robin's mail. is that ok?
Regarding ARM_V7S_ADDR_BITS, I'd like to keep it as is(Don't add cfg),
this macro only is used in ARM_V7S_LVL_SHIFT and checking the value of
ias/oas.
a) ARM_V7S_LVL_SHIFT always expect ARM_V7S_ADDR_BITS is 32.
b) our ias/oas is different(ias is 34 while oas is 35). If we define a
new macro, we need two about this, like:
#define ARM_V7S_IADDR_BITS(cfg) (!arm_v7s_is_mtk_enabled(cfg) ? 32 : 34)
#define ARM_V7S_OADDR_BITS(cfg) (!arm_v7s_is_mtk_enabled(cfg) ? 32 : 35)
and the two will only are used in the checking of ias/oas.
thus it looks unnecessary?
>
> Will
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
2020-09-30 7:06 ` [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek Yong Wu
2020-10-23 11:21 ` Will Deacon
@ 2020-10-23 14:10 ` Robin Murphy
2020-10-26 7:41 ` Yong Wu
1 sibling, 1 reply; 55+ messages in thread
From: Robin Murphy @ 2020-10-23 14:10 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Matthias Brugger, Rob Herring,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
On 2020-09-30 08:06, Yong Wu wrote:
> The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> 34bit.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++---
> drivers/iommu/mtk_iommu.c | 2 +-
> 2 files changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index 8362fdf76657..306bae2755ed 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -50,10 +50,17 @@
> */
> #define ARM_V7S_ADDR_BITS 32
> #define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
> +/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
> +#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6)
This should defined in terms of both lvl and cfg->ias. The formula here
is nothing more than a disgusting trick I made up since a linear
interpolation happened to fit the required numbers. That said, all of
these bits pretending that short-descriptor is a well-defined recursive
format only served to allow the rest of the code to look more like the
LPAE code - IIRC they've already diverged a fair bit since then, so
frankly a lot of this could stand to be unpicked and made considerably
clearer by simply accepting that level 1 and level 2 are different from
each other.
Robin.
> #define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
> #define ARM_V7S_TABLE_SHIFT 10
>
> -#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl))
> +#define ARM_V7S_PTES_PER_LVL(lvl, cfg) ({ \
> + int _lvl = lvl; \
> + !arm_v7s_is_mtk_enabled(cfg) ? \
> + (1 << _ARM_V7S_LVL_BITS(_lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(_lvl));\
> +})
> +
> #define ARM_V7S_TABLE_SIZE(lvl, cfg) \
> (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
>
> @@ -63,7 +70,7 @@
> #define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
> #define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \
> int _l = lvl; \
> - ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> + ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> })
>
> /*
> @@ -755,7 +762,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> {
> struct arm_v7s_io_pgtable *data;
>
> - if (cfg->ias > ARM_V7S_ADDR_BITS)
> + if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
> return NULL;
>
> if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index f6a2e3eb59d2..6e85c9976a33 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
> IO_PGTABLE_QUIRK_TLBI_ON_MAP |
> IO_PGTABLE_QUIRK_ARM_MTK_EXT,
> .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
> - .ias = 32,
> + .ias = 34,
> .oas = 35,
> .tlb = &mtk_iommu_flush_ops,
> .iommu_dev = data->dev,
>
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^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
2020-10-23 14:10 ` Robin Murphy
@ 2020-10-26 7:41 ` Yong Wu
2020-10-26 11:35 ` Robin Murphy
0 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-10-26 7:41 UTC (permalink / raw)
To: Robin Murphy
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, Greg Kroah-Hartman, linux-kernel,
Evan Green, Tomasz Figa, iommu, Rob Herring, linux-mediatek,
Krzysztof Kozlowski, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Fri, 2020-10-23 at 15:10 +0100, Robin Murphy wrote:
> On 2020-09-30 08:06, Yong Wu wrote:
> > The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> > (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> > 34bit.
> >
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > ---
> > drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++---
> > drivers/iommu/mtk_iommu.c | 2 +-
> > 2 files changed, 11 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> > index 8362fdf76657..306bae2755ed 100644
> > --- a/drivers/iommu/io-pgtable-arm-v7s.c
> > +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> > @@ -50,10 +50,17 @@
> > */
> > #define ARM_V7S_ADDR_BITS 32
> > #define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
> > +/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
> > +#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6)
>
> This should defined in terms of both lvl and cfg->ias. The formula here
> is nothing more than a disgusting trick I made up since a linear
> interpolation happened to fit the required numbers. That said, all of
> these bits pretending that short-descriptor is a well-defined recursive
> format only served to allow the rest of the code to look more like the
> LPAE code - IIRC they've already diverged a fair bit since then, so
> frankly a lot of this could stand to be unpicked and made considerably
> clearer by simply accepting that level 1 and level 2 are different from
> each other.
If the formula is not good and make it clearer, How about this?
/*
* We have 32 bits total; 12 bits resolved at level 1, 8 bits at level
2,
-* and 12 bits in a page. With some carefully-chosen coefficients we can
-* hide the ugly inconsistencies behind these macros and at least let
the
-* rest of the code pretend to be somewhat sane.
+* and 12 bits in a page.
+*
+* MediaTek extend 2 bits to reach 34 bits, 14 bits at lvl1 and 8 bits
at lvl2.
*/
-#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
+#define _ARM_V7S_LVL1_BITS_NR(cfg) (((cfg)->ias == 32) ? 12 : 14)
+#define _ARM_V7S_LVL2_BITS_NR 8
+
+#define _ARM_V7S_LVL_BITS(lvl, cfg) \
+ (((lvl) == 1) ? _ARM_V7S_LVL1_BITS_NR(cfg):_ARM_V7S_LVL2_BITS_NR)
> Robin.
>
> > #define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
> > #define ARM_V7S_TABLE_SHIFT 10
> >
> > -#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl))
> > +#define ARM_V7S_PTES_PER_LVL(lvl, cfg) ({ \
> > + int _lvl = lvl; \
> > + !arm_v7s_is_mtk_enabled(cfg) ? \
> > + (1 << _ARM_V7S_LVL_BITS(_lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(_lvl));\
> > +})
> > +
> > #define ARM_V7S_TABLE_SIZE(lvl, cfg) \
> > (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
> >
> > @@ -63,7 +70,7 @@
> > #define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
> > #define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \
> > int _l = lvl; \
> > - ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> > + ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
> > })
> >
> > /*
> > @@ -755,7 +762,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> > {
> > struct arm_v7s_io_pgtable *data;
> >
> > - if (cfg->ias > ARM_V7S_ADDR_BITS)
> > + if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
> > return NULL;
> >
> > if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index f6a2e3eb59d2..6e85c9976a33 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
> > IO_PGTABLE_QUIRK_TLBI_ON_MAP |
> > IO_PGTABLE_QUIRK_ARM_MTK_EXT,
> > .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
> > - .ias = 32,
> > + .ias = 34,
> > .oas = 35,
> > .tlb = &mtk_iommu_flush_ops,
> > .iommu_dev = data->dev,
> >
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^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
2020-10-26 7:41 ` Yong Wu
@ 2020-10-26 11:35 ` Robin Murphy
0 siblings, 0 replies; 55+ messages in thread
From: Robin Murphy @ 2020-10-26 11:35 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, Greg Kroah-Hartman, linux-kernel,
Evan Green, Tomasz Figa, iommu, Rob Herring, linux-mediatek,
Krzysztof Kozlowski, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On 2020-10-26 07:41, Yong Wu wrote:
> On Fri, 2020-10-23 at 15:10 +0100, Robin Murphy wrote:
>> On 2020-09-30 08:06, Yong Wu wrote:
>>> The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
>>> (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
>>> 34bit.
>>>
>>> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
>>> ---
>>> drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++---
>>> drivers/iommu/mtk_iommu.c | 2 +-
>>> 2 files changed, 11 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
>>> index 8362fdf76657..306bae2755ed 100644
>>> --- a/drivers/iommu/io-pgtable-arm-v7s.c
>>> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
>>> @@ -50,10 +50,17 @@
>>> */
>>> #define ARM_V7S_ADDR_BITS 32
>>> #define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
>>> +/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
>>> +#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6)
>>
>> This should defined in terms of both lvl and cfg->ias. The formula here
>> is nothing more than a disgusting trick I made up since a linear
>> interpolation happened to fit the required numbers. That said, all of
>> these bits pretending that short-descriptor is a well-defined recursive
>> format only served to allow the rest of the code to look more like the
>> LPAE code - IIRC they've already diverged a fair bit since then, so
>> frankly a lot of this could stand to be unpicked and made considerably
>> clearer by simply accepting that level 1 and level 2 are different from
>> each other.
>
> If the formula is not good and make it clearer, How about this?
>
>
> /*
> * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level
> 2,
> -* and 12 bits in a page. With some carefully-chosen coefficients we can
> -* hide the ugly inconsistencies behind these macros and at least let
> the
> -* rest of the code pretend to be somewhat sane.
> +* and 12 bits in a page.
> +*
> +* MediaTek extend 2 bits to reach 34 bits, 14 bits at lvl1 and 8 bits
> at lvl2.
> */
>
> -#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
> +#define _ARM_V7S_LVL1_BITS_NR(cfg) (((cfg)->ias == 32) ? 12 : 14)
> +#define _ARM_V7S_LVL2_BITS_NR 8
> +
> +#define _ARM_V7S_LVL_BITS(lvl, cfg) \
> + (((lvl) == 1) ? _ARM_V7S_LVL1_BITS_NR(cfg):_ARM_V7S_LVL2_BITS_NR)
Well, I'd have gone for something really simple and clear like:
#define ARM_V7S_LVL_BITS(lvl, cfg) ((lvl) == 1 ? (cfg)->ias - 20 : 8)
#define ARM_V7S_LVL_SHIFT(lvl) ((lvl) == 1 ? 20 : 12)
Then maybe see if enough of the users could resolve lvl significantly
earlier to make it worth splitting things up further.
Robin.
>>> #define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
>>> #define ARM_V7S_TABLE_SHIFT 10
>>>
>>> -#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl))
>>> +#define ARM_V7S_PTES_PER_LVL(lvl, cfg) ({ \
>>> + int _lvl = lvl; \
>>> + !arm_v7s_is_mtk_enabled(cfg) ? \
>>> + (1 << _ARM_V7S_LVL_BITS(_lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(_lvl));\
>>> +})
>>> +
>>> #define ARM_V7S_TABLE_SIZE(lvl, cfg) \
>>> (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
>>>
>>> @@ -63,7 +70,7 @@
>>> #define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
>>> #define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \
>>> int _l = lvl; \
>>> - ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
>>> + ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
>>> })
>>>
>>> /*
>>> @@ -755,7 +762,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
>>> {
>>> struct arm_v7s_io_pgtable *data;
>>>
>>> - if (cfg->ias > ARM_V7S_ADDR_BITS)
>>> + if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
>>> return NULL;
>>>
>>> if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
>>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
>>> index f6a2e3eb59d2..6e85c9976a33 100644
>>> --- a/drivers/iommu/mtk_iommu.c
>>> +++ b/drivers/iommu/mtk_iommu.c
>>> @@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
>>> IO_PGTABLE_QUIRK_TLBI_ON_MAP |
>>> IO_PGTABLE_QUIRK_ARM_MTK_EXT,
>>> .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
>>> - .ias = 32,
>>> + .ias = 34,
>>> .oas = 35,
>>> .tlb = &mtk_iommu_flush_ops,
>>> .iommu_dev = data->dev,
>>>
>
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v3 12/24] iommu/mediatek: Move hw_init into attach_device
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (10 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 13/24] iommu/mediatek: Add device link for smi-common and m4u Yong Wu
` (12 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
In attach device, it will update the pagetable base address register.
Move the hw_init function also here. Then it only need call
pm_runtime_get/put one time here if m4u has power domain.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 6e85c9976a33..940b7a9191b2 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -122,6 +122,8 @@ struct mtk_iommu_domain {
static const struct iommu_ops mtk_iommu_ops;
+static int mtk_iommu_hw_init(const struct mtk_iommu_data *data);
+
/*
* In M4U 4GB mode, the physical address is remapped as below:
*
@@ -377,12 +379,16 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
{
struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ int ret;
if (!data)
return -ENODEV;
/* Update the pgtable base address register of the M4U HW */
if (!data->m4u_dom) {
+ ret = mtk_iommu_hw_init(data);
+ if (ret)
+ return ret;
data->m4u_dom = dom;
writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
data->base + REG_MMU_PT_BASE_ADDR);
@@ -705,10 +711,6 @@ static int mtk_iommu_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, data);
- ret = mtk_iommu_hw_init(data);
- if (ret)
- return ret;
-
ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
"mtk-iommu.%pa", &ioaddr);
if (ret)
--
2.18.0
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 13/24] iommu/mediatek: Add device link for smi-common and m4u
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (11 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 12/24] iommu/mediatek: Move hw_init into attach_device Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 14/24] iommu/mediatek: Add pm runtime callback Yong Wu
` (11 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
In the lastest SoC, M4U has its special power domain. thus, If the engine
begin to work, it should help enable the power for M4U firstly.
Currently if the engine work, it always enable the power/clocks for
smi-larbs/smi-common. This patch adds device_link for smi-common and M4U.
then, if smi-common power is enabled, the M4U power also is powered on
automatically.
Normally M4U connect with several smi-larbs and their smi-common always
are the same, In this patch it get smi-common dev from the first smi-larb
device(i==0), then add the device_link only while m4u has power-domain.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 24 +++++++++++++++++++++++-
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 940b7a9191b2..5625458b21ba 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -20,6 +20,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <asm/barrier.h>
@@ -681,7 +682,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
return larb_nr;
for (i = 0; i < larb_nr; i++) {
- struct device_node *larbnode;
+ struct device_node *larbnode, *smicomm_node;
struct platform_device *plarbdev;
u32 id;
@@ -707,6 +708,15 @@ static int mtk_iommu_probe(struct platform_device *pdev)
component_match_add_release(dev, &match, release_of,
compare_of, larbnode);
+ if (!i) {
+ smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
+ if (!smicomm_node)
+ return -EINVAL;
+
+ plarbdev = of_find_device_by_node(smicomm_node);
+ of_node_put(smicomm_node);
+ data->smicomm_dev = &plarbdev->dev;
+ }
}
platform_set_drvdata(pdev, data);
@@ -729,6 +739,16 @@ static int mtk_iommu_probe(struct platform_device *pdev)
if (!iommu_present(&platform_bus_type))
bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
+ if (dev->pm_domain) {
+ struct device_link *link;
+
+ link = device_link_add(data->smicomm_dev, dev,
+ DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
+ if (!link) {
+ dev_err(dev, "Unable link %s.\n", dev_name(data->smicomm_dev));
+ return -EINVAL;
+ }
+ }
return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
}
@@ -743,6 +763,8 @@ static int mtk_iommu_remove(struct platform_device *pdev)
bus_set_iommu(&platform_bus_type, NULL);
clk_disable_unprepare(data->bclk);
+ if (pdev->dev.pm_domain)
+ device_link_remove(data->smicomm_dev, &pdev->dev);
devm_free_irq(&pdev->dev, data->irq, data);
component_master_del(&pdev->dev, &mtk_iommu_com_ops);
return 0;
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index a2e2c844b96e..ae7909815cdb 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -67,6 +67,7 @@ struct mtk_iommu_data {
struct iommu_device iommu;
const struct mtk_iommu_plat_data *plat_data;
+ struct device *smicomm_dev;
struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 14/24] iommu/mediatek: Add pm runtime callback
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (12 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 13/24] iommu/mediatek: Add device link for smi-common and m4u Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 15/24] iommu/mediatek: Add power-domain operation Yong Wu
` (10 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
This patch adds pm runtime callback.
In pm runtime case, all the registers backup/restore and bclk are
controlled in the pm_runtime callback, then pm_suspend is not needed in
this case.
runtime PM is disabled when suspend, thus we call
pm_runtime_status_suspended instead of pm_runtime_suspended.
And, m4u doesn't have its special pm runtime domain in previous SoC, in
this case dev->power.runtime_status is RPM_SUSPENDED defaultly, thus add
a "dev->pm_domain" checking for the SoC that has pm runtime domain.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5625458b21ba..052eb72acf69 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -770,7 +770,7 @@ static int mtk_iommu_remove(struct platform_device *pdev)
return 0;
}
-static int __maybe_unused mtk_iommu_suspend(struct device *dev)
+static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
struct mtk_iommu_suspend_reg *reg = &data->reg;
@@ -788,7 +788,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
return 0;
}
-static int __maybe_unused mtk_iommu_resume(struct device *dev)
+static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
{
struct mtk_iommu_data *data = dev_get_drvdata(dev);
struct mtk_iommu_suspend_reg *reg = &data->reg;
@@ -815,7 +815,25 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
return 0;
}
+static int __maybe_unused mtk_iommu_suspend(struct device *dev)
+{
+ /* runtime PM is disabled when suspend in pm_runtime case. */
+ if (dev->pm_domain && pm_runtime_status_suspended(dev))
+ return 0;
+
+ return mtk_iommu_runtime_suspend(dev);
+}
+
+static int __maybe_unused mtk_iommu_resume(struct device *dev)
+{
+ if (dev->pm_domain && pm_runtime_status_suspended(dev))
+ return 0;
+
+ return mtk_iommu_runtime_resume(dev);
+}
+
static const struct dev_pm_ops mtk_iommu_pm_ops = {
+ SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
};
--
2.18.0
_______________________________________________
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 15/24] iommu/mediatek: Add power-domain operation
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (13 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 14/24] iommu/mediatek: Add pm runtime callback Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 16/24] iommu/mediatek: Add iova reserved function Yong Wu
` (9 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
In the previous SoC, the M4U HW is in the EMI power domain which is
always on. the latest M4U is in the display power domain which may be
turned on/off, thus we have to add pm_runtime interface for it.
When the engine work, the engine always enable the power and clocks for
smi-larb/smi-common, then the M4U's power will always be powered on
automatically via the device link with smi-common.
Note: we don't enable the M4U power in iommu_map/unmap for tlb flush.
If its power already is on, of course it is ok. if the power is off,
the main tlb will be reset while M4U power on, thus the tlb flush while
m4u power off is unnecessary, just skip it.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 052eb72acf69..1e6e6d3fa7f1 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -196,6 +196,10 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
u32 tmp;
for_each_m4u(data) {
+ /* skip tlb flush when pm is not active. */
+ if (!pm_runtime_active(data->dev))
+ continue;
+
spin_lock_irqsave(&data->tlb_lock, flags);
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
data->base + data->plat_data->inv_sel_reg);
@@ -380,6 +384,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
{
struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct device *m4udev = data->dev;
int ret;
if (!data)
@@ -387,12 +392,18 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
/* Update the pgtable base address register of the M4U HW */
if (!data->m4u_dom) {
+ ret = pm_runtime_get_sync(m4udev);
+ if (ret < 0)
+ return ret;
ret = mtk_iommu_hw_init(data);
- if (ret)
+ if (ret) {
+ pm_runtime_put(m4udev);
return ret;
+ }
data->m4u_dom = dom;
writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
data->base + REG_MMU_PT_BASE_ADDR);
+ pm_runtime_put(m4udev);
}
mtk_iommu_config(data, dev, true);
@@ -742,10 +753,13 @@ static int mtk_iommu_probe(struct platform_device *pdev)
if (dev->pm_domain) {
struct device_link *link;
+ pm_runtime_enable(dev);
+
link = device_link_add(data->smicomm_dev, dev,
DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
if (!link) {
dev_err(dev, "Unable link %s.\n", dev_name(data->smicomm_dev));
+ pm_runtime_disable(dev);
return -EINVAL;
}
}
@@ -763,8 +777,10 @@ static int mtk_iommu_remove(struct platform_device *pdev)
bus_set_iommu(&platform_bus_type, NULL);
clk_disable_unprepare(data->bclk);
- if (pdev->dev.pm_domain)
+ if (pdev->dev.pm_domain) {
device_link_remove(data->smicomm_dev, &pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ }
devm_free_irq(&pdev->dev, data->irq, data);
component_master_del(&pdev->dev, &mtk_iommu_com_ops);
return 0;
@@ -796,6 +812,9 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
void __iomem *base = data->base;
int ret;
+ /* Avoid first resume to affect the default value of registers below. */
+ if (!m4u_dom)
+ return 0;
ret = clk_prepare_enable(data->bclk);
if (ret) {
dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
@@ -809,9 +828,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
- if (m4u_dom)
- writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
- base + REG_MMU_PT_BASE_ADDR);
+ writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR);
return 0;
}
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 16/24] iommu/mediatek: Add iova reserved function
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (14 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 15/24] iommu/mediatek: Add power-domain operation Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 17/24] iommu/mediatek: Add single domain Yong Wu
` (8 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
For multiple iommu_domains, we need to reserve some iova regions. Take a
example, If the default iova region is 0 ~ 4G, but the 0x4000_0000 ~
0x43ff_ffff is only for the special CCU0 domain. Thus we should exclude
this region for the default iova region.
This patch adds iova reserved flow. It's a preparing patch for supporting
multi-domain.
Signed-off-by: Anan sun <anan.sun@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 28 ++++++++++++++++++++++++++++
drivers/iommu/mtk_iommu.h | 5 +++++
2 files changed, 33 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 1e6e6d3fa7f1..8e2a8e29d13c 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -153,6 +153,11 @@ static LIST_HEAD(m4ulist); /* List all the M4U HWs */
#define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list)
+struct mtk_iommu_iova_region {
+ dma_addr_t iova_base;
+ unsigned long long size;
+};
+
/*
* There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
* for the performance.
@@ -539,6 +544,27 @@ static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
return iommu_fwspec_add_ids(dev, args->args, 1);
}
+static void mtk_iommu_get_resv_regions(struct device *dev,
+ struct list_head *head)
+{
+ struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
+ const struct mtk_iommu_iova_region *resv;
+ struct iommu_resv_region *region;
+ int prot = IOMMU_WRITE | IOMMU_READ;
+ unsigned int i;
+
+ for (i = 0; i < data->plat_data->iova_region_nr; i++) {
+ resv = data->plat_data->iova_region + i;
+
+ region = iommu_alloc_resv_region(resv->iova_base, resv->size,
+ prot, IOMMU_RESV_RESERVED);
+ if (!region)
+ return;
+
+ list_add_tail(®ion->list, head);
+ }
+}
+
static const struct iommu_ops mtk_iommu_ops = {
.domain_alloc = mtk_iommu_domain_alloc,
.domain_free = mtk_iommu_domain_free,
@@ -553,6 +579,8 @@ static const struct iommu_ops mtk_iommu_ops = {
.release_device = mtk_iommu_release_device,
.device_group = mtk_iommu_device_group,
.of_xlate = mtk_iommu_of_xlate,
+ .get_resv_regions = mtk_iommu_get_resv_regions,
+ .put_resv_regions = generic_iommu_put_resv_regions,
.pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index ae7909815cdb..d45c13c9d324 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -44,10 +44,15 @@ enum mtk_iommu_plat {
M4U_MT8183,
};
+struct mtk_iommu_iova_region;
+
struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
u32 flags;
u32 inv_sel_reg;
+
+ unsigned int iova_region_nr;
+ const struct mtk_iommu_iova_region *iova_region;
unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
};
--
2.18.0
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 17/24] iommu/mediatek: Add single domain
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (15 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 16/24] iommu/mediatek: Add iova reserved function Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 18/24] iommu/mediatek: Support master use iova over 32bit Yong Wu
` (7 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Defaultly the iova range is 0-4G. here we add a single-domain(0-4G)
for the previous SoC. this also is a preparing patch for supporting
multi-domains.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 8e2a8e29d13c..87ca4f47e494 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -158,6 +158,10 @@ struct mtk_iommu_iova_region {
unsigned long long size;
};
+static const struct mtk_iommu_iova_region single_domain[] = {
+ {.iova_base = 0, .size = SZ_4G},
+};
+
/*
* There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
* for the performance.
@@ -886,6 +890,8 @@ static const struct mtk_iommu_plat_data mt2712_data = {
.m4u_plat = M4U_MT2712,
.flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
+ .iova_region = single_domain,
+ .iova_region_nr = ARRAY_SIZE(single_domain),
.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
};
@@ -893,6 +899,8 @@ static const struct mtk_iommu_plat_data mt6779_data = {
.m4u_plat = M4U_MT6779,
.flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,
.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
+ .iova_region = single_domain,
+ .iova_region_nr = ARRAY_SIZE(single_domain),
.larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
};
@@ -900,6 +908,8 @@ static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
+ .iova_region = single_domain,
+ .iova_region_nr = ARRAY_SIZE(single_domain),
.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
};
@@ -907,6 +917,8 @@ static const struct mtk_iommu_plat_data mt8183_data = {
.m4u_plat = M4U_MT8183,
.flags = RESET_AXI,
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
+ .iova_region = single_domain,
+ .iova_region_nr = ARRAY_SIZE(single_domain),
.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
};
--
2.18.0
_______________________________________________
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 18/24] iommu/mediatek: Support master use iova over 32bit
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (16 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 17/24] iommu/mediatek: Add single domain Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-10-06 7:18 ` Krzysztof Kozlowski
2020-09-30 7:06 ` [PATCH v3 19/24] iommu/mediatek: Support up to 34bit iova in tlb flush Yong Wu
` (6 subsequent siblings)
24 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
After extending v7s, our pagetable already support iova reach
16GB(34bit). the master got the iova via dma_alloc_attrs may reach
34bits, but its HW register still is 32bit. then how to set the
bit32/bit33 iova? this depend on a SMI larb setting(bank_sel).
we separate whole 16GB iova to four banks:
bank: 0: 0~4G; 1: 4~8G; 2: 8-12G; 3: 12-16G;
The bank number is (iova >> 32).
We will preassign which bank the larbs belong to. currently we don't
have a interface for master to adjust its bank number.
Each a bank is a iova_region which is a independent iommu-domain.
the iova range for each iommu-domain can't cross 4G.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 12 +++++++++---
drivers/memory/mtk-smi.c | 7 +++++++
include/soc/mediatek/smi.h | 1 +
3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 87ca4f47e494..2f26a8242428 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -303,17 +303,23 @@ static void mtk_iommu_config(struct mtk_iommu_data *data,
struct device *dev, bool enable)
{
struct mtk_smi_larb_iommu *larb_mmu;
- unsigned int larbid, portid;
+ unsigned int larbid, portid, domid;
struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+ const struct mtk_iommu_iova_region *region;
int i;
for (i = 0; i < fwspec->num_ids; ++i) {
larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
+ domid = MTK_M4U_TO_DOM(fwspec->ids[i]);
+
larb_mmu = &data->larb_imu[larbid];
+ region = data->plat_data->iova_region + domid;
+ larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
- dev_dbg(dev, "%s iommu port: %d\n",
- enable ? "enable" : "disable", portid);
+ dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n",
+ enable ? "enable" : "disable", dev_name(larb_mmu->dev),
+ portid, domid, larb_mmu->bank[portid]);
if (enable)
larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index ec83f1ac48b1..e94c99ca2883 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -41,6 +41,10 @@
/* mt2712 */
#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
#define F_MMU_EN BIT(0)
+#define BANK_SEL(id) ({ \
+ u32 _id = (id) & 0x3; \
+ (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
+})
/* SMI COMMON */
#define SMI_BUS_SEL 0x220
@@ -85,6 +89,7 @@ struct mtk_smi_larb { /* larb: local arbiter */
const struct mtk_smi_larb_gen *larb_gen;
int larbid;
u32 *mmu;
+ unsigned char *bank;
};
static int mtk_smi_clk_enable(const struct mtk_smi *smi)
@@ -151,6 +156,7 @@ mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
if (dev == larb_mmu[i].dev) {
larb->larbid = i;
larb->mmu = &larb_mmu[i].mmu;
+ larb->bank = larb_mmu[i].bank;
return 0;
}
}
@@ -169,6 +175,7 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
reg |= F_MMU_EN;
+ reg |= BANK_SEL(larb->bank[i]);
writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
}
}
diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
index 9371bf572ab8..4cf445dbbdaa 100644
--- a/include/soc/mediatek/smi.h
+++ b/include/soc/mediatek/smi.h
@@ -16,6 +16,7 @@
struct mtk_smi_larb_iommu {
struct device *dev;
unsigned int mmu;
+ unsigned char bank[32];
};
/*
--
2.18.0
_______________________________________________
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v3 18/24] iommu/mediatek: Support master use iova over 32bit
2020-09-30 7:06 ` [PATCH v3 18/24] iommu/mediatek: Support master use iova over 32bit Yong Wu
@ 2020-10-06 7:18 ` Krzysztof Kozlowski
0 siblings, 0 replies; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-06 7:18 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:41PM +0800, Yong Wu wrote:
> After extending v7s, our pagetable already support iova reach
> 16GB(34bit). the master got the iova via dma_alloc_attrs may reach
> 34bits, but its HW register still is 32bit. then how to set the
> bit32/bit33 iova? this depend on a SMI larb setting(bank_sel).
>
> we separate whole 16GB iova to four banks:
> bank: 0: 0~4G; 1: 4~8G; 2: 8-12G; 3: 12-16G;
> The bank number is (iova >> 32).
>
> We will preassign which bank the larbs belong to. currently we don't
> have a interface for master to adjust its bank number.
>
> Each a bank is a iova_region which is a independent iommu-domain.
> the iova range for each iommu-domain can't cross 4G.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 12 +++++++++---
> drivers/memory/mtk-smi.c | 7 +++++++
> include/soc/mediatek/smi.h | 1 +
> 3 files changed, 17 insertions(+), 3 deletions(-)
For the memory part:
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v3 19/24] iommu/mediatek: Support up to 34bit iova in tlb flush
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (17 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 18/24] iommu/mediatek: Support master use iova over 32bit Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 20/24] iommu/mediatek: Support report iova 34bit translation fault in ISR Yong Wu
` (5 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
If the iova is 34bit, the iova[32][33] is the bit0/1 in the tlb flush
register. Add a new macro for this.
there is a minor change unrelated with this patch. it also use the new
macro.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 2f26a8242428..a2e519c86ce9 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -125,6 +125,9 @@ static const struct iommu_ops mtk_iommu_ops;
static int mtk_iommu_hw_init(const struct mtk_iommu_data *data);
+#define MTK_IOMMU_ADDR(addr) ({unsigned long _addr = addr; \
+ (lower_32_bits(_addr) | upper_32_bits(_addr)); })
+
/*
* In M4U 4GB mode, the physical address is remapped as below:
*
@@ -213,8 +216,9 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
data->base + data->plat_data->inv_sel_reg);
- writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
- writel_relaxed(iova + size - 1,
+ writel_relaxed(MTK_IOMMU_ADDR(iova),
+ data->base + REG_MMU_INVLD_START_A);
+ writel_relaxed(MTK_IOMMU_ADDR(iova + size - 1),
data->base + REG_MMU_INVLD_END_A);
writel_relaxed(F_MMU_INV_RANGE,
data->base + REG_MMU_INVALIDATE);
@@ -634,8 +638,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
if (data->plat_data->m4u_plat == M4U_MT8173)
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else
- regval = lower_32_bits(data->protect_base) |
- upper_32_bits(data->protect_base);
+ regval = MTK_IOMMU_ADDR(data->protect_base);
writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
if (data->enable_4GB &&
--
2.18.0
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 20/24] iommu/mediatek: Support report iova 34bit translation fault in ISR
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (18 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 19/24] iommu/mediatek: Support up to 34bit iova in tlb flush Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 21/24] iommu/mediatek: Add support for multi domain Yong Wu
` (4 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
If the iova is over 32bit, the fault status register bit is a little
different. Add a flag for the special register bits.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index a2e519c86ce9..16760e318648 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -4,6 +4,7 @@
* Author: Yong Wu <yong.wu@mediatek.com>
*/
#include <linux/memblock.h>
+#include <linux/bitfield.h>
#include <linux/bug.h>
#include <linux/clk.h>
#include <linux/component.h>
@@ -87,6 +88,9 @@
#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
#define REG_MMU0_FAULT_VA 0x13c
+#define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)
+#define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)
+#define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)
#define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
#define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
@@ -110,6 +114,7 @@
#define OUT_ORDER_WR_EN BIT(4)
#define HAS_SUB_COMM BIT(5)
#define WR_THROT_EN BIT(6)
+#define IOVA_34_EN BIT(7)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x))
@@ -258,8 +263,9 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
{
struct mtk_iommu_data *data = dev_id;
struct mtk_iommu_domain *dom = data->m4u_dom;
- u32 int_state, regval, fault_iova, fault_pa;
unsigned int fault_larb, fault_port, sub_comm = 0;
+ u32 int_state, regval, va34_32, pa34_32;
+ u64 fault_iova, fault_pa;
bool layer, write;
/* Read error info from registers */
@@ -275,6 +281,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
}
layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) {
+ va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
+ pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
+ fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
+ fault_iova |= (u64)va34_32 << 32;
+ fault_pa |= (u64)pa34_32 << 32;
+ }
+
fault_port = F_MMU_INT_ID_PORT_ID(regval);
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
fault_larb = F_MMU_INT_ID_COMM_ID(regval);
@@ -288,7 +302,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
dev_err_ratelimited(
data->dev,
- "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
+ "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n",
int_state, fault_iova, fault_pa, fault_larb, fault_port,
layer, write ? "write" : "read");
}
--
2.18.0
_______________________________________________
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 21/24] iommu/mediatek: Add support for multi domain
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (19 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 20/24] iommu/mediatek: Support report iova 34bit translation fault in ISR Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 22/24] iommu/mediatek: Adjust the structure Yong Wu
` (3 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Some HW IP(ex: CCU) require the special iova range. That means the
iova got from dma_alloc_attrs for that devices must locate in his
special range. In this patch, we allocate a special iova_range for
each a special requirement and create each a iommu domain for each
a iova_range.
meanwhile we still use one pagetable which support 16GB iova.
After this patch, If the iova range of a master is over 4G, the master
should:
a) Declare its special dma_ranges in its dtsi node. For example, If we
preassign the iova 4G-8G for vcodec, then the vcodec dtsi node should
add this:
/*
* iova start at 0x1_0000_0000, pa still start at 0x4000_0000
* size is 0x1_0000_0000.
*/
dma-ranges = <0x1 0x0 0x0 0x40000000 0x1 0x0>; /* 4G ~ 8G */
Note: we don't have a actual bus concept here. the master doesn't have its
special parent node, thus this dma-ranges can only be put in the master's
node.
b) Update the dma_mask:
dma_set_mask_and_coherent(dev, DMA_BIT_MASK(33));
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 47 +++++++++++++++++++++++++++++++--------
drivers/iommu/mtk_iommu.h | 3 ++-
2 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 16760e318648..1d5d3e76d2d1 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -350,6 +350,14 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
{
struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ /* Use the exist domain as there is only one m4u pgtable here. */
+ if (data->m4u_dom) {
+ dom->iop = data->m4u_dom->iop;
+ dom->cfg = data->m4u_dom->cfg;
+ dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap;
+ return 0;
+ }
+
dom->cfg = (struct io_pgtable_cfg) {
.quirks = IO_PGTABLE_QUIRK_ARM_NS |
IO_PGTABLE_QUIRK_NO_PERMS |
@@ -375,6 +383,8 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
{
+ struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ const struct mtk_iommu_iova_region *region;
struct mtk_iommu_domain *dom;
if (type != IOMMU_DOMAIN_DMA)
@@ -390,8 +400,9 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
if (mtk_iommu_domain_finalise(dom))
goto put_dma_cookie;
- dom->domain.geometry.aperture_start = 0;
- dom->domain.geometry.aperture_end = DMA_BIT_MASK(32);
+ region = data->plat_data->iova_region + data->cur_domid;
+ dom->domain.geometry.aperture_start = region->iova_base;
+ dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
dom->domain.geometry.force_aperture = true;
return &dom->domain;
@@ -535,19 +546,31 @@ static void mtk_iommu_release_device(struct device *dev)
static struct iommu_group *mtk_iommu_device_group(struct device *dev)
{
struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+ struct iommu_group *group;
+ int domid;
if (!data)
return ERR_PTR(-ENODEV);
- /* All the client devices are in the same m4u iommu-group */
- if (!data->m4u_group) {
- data->m4u_group = iommu_group_alloc();
- if (IS_ERR(data->m4u_group))
+ domid = MTK_M4U_TO_DOM(fwspec->ids[0]);
+ if (domid >= data->plat_data->iova_region_nr) {
+ dev_err(dev, "iommu domain id(%d/%d) is error.\n", domid,
+ data->plat_data->iova_region_nr);
+ return ERR_PTR(-EINVAL);
+ }
+
+ group = data->m4u_group[domid];
+ if (!group) {
+ group = iommu_group_alloc();
+ if (IS_ERR(group))
dev_err(dev, "Failed to allocate M4U IOMMU group\n");
+ data->m4u_group[domid] = group;
} else {
- iommu_group_ref_get(data->m4u_group);
+ iommu_group_ref_get(group);
}
- return data->m4u_group;
+ data->cur_domid = domid;
+ return group;
}
static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
@@ -576,14 +599,20 @@ static void mtk_iommu_get_resv_regions(struct device *dev,
struct list_head *head)
{
struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
- const struct mtk_iommu_iova_region *resv;
+ const struct mtk_iommu_iova_region *resv, *curdom;
struct iommu_resv_region *region;
int prot = IOMMU_WRITE | IOMMU_READ;
unsigned int i;
+ curdom = data->plat_data->iova_region + data->cur_domid;
for (i = 0; i < data->plat_data->iova_region_nr; i++) {
resv = data->plat_data->iova_region + i;
+ /* Only reserve when the region is in the current domain */
+ if (resv->iova_base <= curdom->iova_base ||
+ resv->iova_base + resv->size >= curdom->iova_base + curdom->size)
+ continue;
+
region = iommu_alloc_resv_region(resv->iova_base, resv->size,
prot, IOMMU_RESV_RESERVED);
if (!region)
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index d45c13c9d324..5e346464cdf8 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -66,7 +66,7 @@ struct mtk_iommu_data {
phys_addr_t protect_base; /* protect memory base */
struct mtk_iommu_suspend_reg reg;
struct mtk_iommu_domain *m4u_dom;
- struct iommu_group *m4u_group;
+ struct iommu_group *m4u_group[MTK_M4U_DOM_NR_MAX];
bool enable_4GB;
spinlock_t tlb_lock; /* lock for tlb range flush */
@@ -76,6 +76,7 @@ struct mtk_iommu_data {
struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */
+ unsigned int cur_domid;
struct list_head list;
struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
};
--
2.18.0
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 22/24] iommu/mediatek: Adjust the structure
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (20 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 21/24] iommu/mediatek: Add support for multi domain Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 23/24] iommu/mediatek: Add mt8192 support Yong Wu
` (2 subsequent siblings)
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Add "struct mtk_iommu_data *" in the "struct mtk_iommu_domain",
reduce the call mtk_iommu_get_m4u_data().
No functional change.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 1d5d3e76d2d1..7f8d39f8ac29 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -123,6 +123,7 @@ struct mtk_iommu_domain {
struct io_pgtable_cfg cfg;
struct io_pgtable_ops *iop;
+ struct mtk_iommu_data *data;
struct iommu_domain domain;
};
@@ -348,7 +349,7 @@ static void mtk_iommu_config(struct mtk_iommu_data *data,
static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
{
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ struct mtk_iommu_data *data = dom->data;
/* Use the exist domain as there is only one m4u pgtable here. */
if (data->m4u_dom) {
@@ -397,6 +398,7 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
if (iommu_get_dma_cookie(&dom->domain))
goto free_dom;
+ dom->data = data;
if (mtk_iommu_domain_finalise(dom))
goto put_dma_cookie;
@@ -469,10 +471,9 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
{
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
/* The "4GB mode" M4U physically can not use the lower remap of Dram. */
- if (data->enable_4GB)
+ if (dom->data->enable_4GB)
paddr |= BIT_ULL(32);
/* Synchronize with the tlb_lock */
@@ -490,31 +491,32 @@ static size_t mtk_iommu_unmap(struct iommu_domain *domain,
static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
{
- mtk_iommu_tlb_flush_all(mtk_iommu_get_m4u_data());
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+
+ mtk_iommu_tlb_flush_all(dom->data);
}
static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
struct iommu_iotlb_gather *gather)
{
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
size_t length = gather->end - gather->start;
if (gather->start == ULONG_MAX)
return;
mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize,
- data);
+ dom->data);
}
static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
dma_addr_t iova)
{
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
phys_addr_t pa;
pa = dom->iop->iova_to_phys(dom->iop, iova);
- if (data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
+ if (dom->data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
pa &= ~BIT_ULL(32);
return pa;
--
2.18.0
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^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 23/24] iommu/mediatek: Add mt8192 support
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (21 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 22/24] iommu/mediatek: Adjust the structure Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 24/24] memory: mtk-smi: " Yong Wu
2020-10-26 20:08 ` [PATCH v3 00/24] MT8192 IOMMU support Krzysztof Kozlowski
24 siblings, 0 replies; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Add mt8192 iommu support.
For multi domain, Add 1M gap for the vdec domain size. That is because
vdec HW has a end address register which require (start_addr +
len) rather than (start_addr + len - 1). Take a example, if the start_addr
is 0xfff00000, size is 0x100000, then the end_address is 0xfff00000 +
0x100000 = 0x1 0000 0000. but the register only is 32bit. thus HW will get
the end address is 0. To avoid this issue, I add 1M gap for this.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 22 ++++++++++++++++++++++
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 7f8d39f8ac29..8bf5d4370792 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -171,6 +171,16 @@ static const struct mtk_iommu_iova_region single_domain[] = {
{.iova_base = 0, .size = SZ_4G},
};
+static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
+ { .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */
+ #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
+ { .iova_base = SZ_4G, .size = SZ_4G - SZ_1M}, /* vdec: 4G ~ 8G gap: 1M */
+ { .iova_base = SZ_4G * 2, .size = SZ_4G - SZ_1M}, /* CAM/MDP: 8G ~ 12G */
+ { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
+ { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
+ #endif
+};
+
/*
* There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
* for the performance.
@@ -976,11 +986,23 @@ static const struct mtk_iommu_plat_data mt8183_data = {
.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
};
+static const struct mtk_iommu_plat_data mt8192_data = {
+ .m4u_plat = M4U_MT8192,
+ .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
+ WR_THROT_EN | IOVA_34_EN,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
+ .iova_region = mt8192_multi_dom,
+ .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
+ {0, 14, 16}, {0, 13, 18, 17}},
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
+ { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 5e346464cdf8..d2702eda25d4 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -42,6 +42,7 @@ enum mtk_iommu_plat {
M4U_MT6779,
M4U_MT8173,
M4U_MT8183,
+ M4U_MT8192,
};
struct mtk_iommu_iova_region;
--
2.18.0
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* [PATCH v3 24/24] memory: mtk-smi: Add mt8192 support
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (22 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 23/24] iommu/mediatek: Add mt8192 support Yong Wu
@ 2020-09-30 7:06 ` Yong Wu
2020-10-02 11:15 ` Krzysztof Kozlowski
2020-10-26 20:08 ` [PATCH v3 00/24] MT8192 IOMMU support Krzysztof Kozlowski
24 siblings, 1 reply; 55+ messages in thread
From: Yong Wu @ 2020-09-30 7:06 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Rob Herring, Robin Murphy,
Krzysztof Kozlowski, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, srv_heupstream,
chao.hao, kernel-team, linux-kernel, Evan Green, Tomasz Figa,
iommu, linux-mediatek, ming-fan.chen, anan.sun,
Greg Kroah-Hartman, linux-arm-kernel
Add mt8192 smi support.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/memory/mtk-smi.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index e94c99ca2883..0ec3eff4d92d 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -261,6 +261,10 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
/* IPU0 | IPU1 | CCU */
};
+static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
+ .config_port = mtk_smi_larb_config_port_gen2_general,
+};
+
static const struct of_device_id mtk_smi_larb_of_ids[] = {
{
.compatible = "mediatek,mt8173-smi-larb",
@@ -282,6 +286,10 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = {
.compatible = "mediatek,mt8183-smi-larb",
.data = &mtk_smi_larb_mt8183
},
+ {
+ .compatible = "mediatek,mt8192-smi-larb",
+ .data = &mtk_smi_larb_mt8192
+ },
{}
};
@@ -421,6 +429,13 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
F_MMU1_LARB(7),
};
+static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
+ .gen = MTK_SMI_GEN2,
+ .has_gals = true,
+ .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
+ F_MMU1_LARB(6),
+};
+
static const struct of_device_id mtk_smi_common_of_ids[] = {
{
.compatible = "mediatek,mt8173-smi-common",
@@ -442,6 +457,10 @@ static const struct of_device_id mtk_smi_common_of_ids[] = {
.compatible = "mediatek,mt8183-smi-common",
.data = &mtk_smi_common_mt8183,
},
+ {
+ .compatible = "mediatek,mt8192-smi-common",
+ .data = &mtk_smi_common_mt8192,
+ },
{}
};
--
2.18.0
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v3 24/24] memory: mtk-smi: Add mt8192 support
2020-09-30 7:06 ` [PATCH v3 24/24] memory: mtk-smi: " Yong Wu
@ 2020-10-02 11:15 ` Krzysztof Kozlowski
0 siblings, 0 replies; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-02 11:15 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:47PM +0800, Yong Wu wrote:
> Add mt8192 smi support.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> ---
> drivers/memory/mtk-smi.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
Does it depend on any of the previous patches (so can it be applied
independently)?
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v3 00/24] MT8192 IOMMU support
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
` (23 preceding siblings ...)
2020-09-30 7:06 ` [PATCH v3 24/24] memory: mtk-smi: " Yong Wu
@ 2020-10-26 20:08 ` Krzysztof Kozlowski
24 siblings, 0 replies; 55+ messages in thread
From: Krzysztof Kozlowski @ 2020-10-26 20:08 UTC (permalink / raw)
To: Yong Wu
Cc: youlin.pei, devicetree, kernel-team, Nicolas Boichat,
srv_heupstream, chao.hao, Robin Murphy, Greg Kroah-Hartman,
linux-kernel, Evan Green, Tomasz Figa, iommu, Rob Herring,
linux-mediatek, Matthias Brugger, ming-fan.chen, anan.sun,
Will Deacon, linux-arm-kernel
On Wed, Sep 30, 2020 at 03:06:23PM +0800, Yong Wu wrote:
> This patch mainly adds support for mt8192 IOMMU and SMI.
>
> mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> table format. The M4U-SMI HW diagram is as below:
>
> EMI
> |
> M4U
> |
> ------------
> SMI Common
> ------------
> |
> +-------+------+------+----------------------+-------+
> | | | | ...... | |
> | | | | | |
> larb0 larb1 larb2 larb4 ...... larb19 larb20
> disp0 disp1 mdp vdec IPE IPE
>
> All the connections are HW fixed, SW can NOT adjust it.
>
> Comparing with the preview SoC, this patchset mainly adds two new functions:
> a) add iova 34 bits support.
> b) add multi domains support since several HW has the special iova
> region requirement.
>
> this patchset depend on v5.9-rc1.
Hi,
I think there will be v4 of this, right? If yes, please also describe
the dependencies between the patches. If the entire patchset is strictly
ordered, then mention this as well.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 55+ messages in thread