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From: Will Deacon <will@kernel.org>
To: Kunkun Jiang <jiangkunkun@huawei.com>
Cc: wanghaibin.wang@huawei.com, iommu@lists.linux-foundation.org,
	robin.murphy@arm.com, zhukeqian1@huawei.com
Subject: Re: Some questions about arm_lpae_install_table
Date: Tue, 3 Nov 2020 09:11:30 +0000	[thread overview]
Message-ID: <20201103091130.GA4403@willie-the-truck> (raw)
In-Reply-To: <6778678e-df81-f7e2-235d-6390ff6384ac@huawei.com>

On Tue, Nov 03, 2020 at 11:00:27AM +0800, Kunkun Jiang wrote:
> Recently, I have read and learned the code related to io-pgtable-arm.c.
> There
> are two question on arm_lpae_install_table.
> 
> 1、the first
> 
> > static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table,
> >                                              arm_lpae_iopte *ptep,
> >                                              arm_lpae_iopte curr,
> >                                              struct io_pgtable_cfg *cfg)
> > {
> >         arm_lpae_iopte old, new;
> > 
> >         new = __pa(table) | ARM_LPAE_PTE_TYPE_TABLE;
> >         if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
> >                 new |= ARM_LPAE_PTE_NSTABLE;
> > 
> >        /*
> >          * Ensure the table itself is visible before its PTE can be.
> >          * Whilst we could get away with cmpxchg64_release below, this
> >          * doesn't have any ordering semantics when !CONFIG_SMP.
> >          */
> >         dma_wmb();
> > 
> >         old = cmpxchg64_relaxed(ptep, curr, new);
> > 
> >         if (cfg->coherent_walk || (old & ARM_LPAE_PTE_SW_SYNC))
> >                 return old;
> > 
> >         /* Even if it's not ours, there's no point waiting; just kick it
> > */
> >         __arm_lpae_sync_pte(ptep, cfg);
> >         if (old == curr)
> >                 WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC);
> > 
> >         return old;
> > }
> 
> If another thread changes the ptep between cmpxchg64_relaxed and
> WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC), the operation
> WRITE_ONCE will overwrite the change.

Can you please provide an example of a code path where this happens? The
idea is that CPUs can race on the cmpxchg(), but there will only be one
winner.

> 2、the second
> 
> > for (i = 0; i < tablesz / sizeof(pte); i++, blk_paddr += split_sz) {
> >                 /* Unmap! */
> >                 if (i == unmap_idx)
> > continue;
> > 
> >                 __arm_lpae_init_pte(data, blk_paddr, pte, lvl,
> > &tablep[i]);
> > }
> > 
> > pte = arm_lpae_install_table(tablep, ptep, blk_pte, cfg);
> 
> When altering a translation table descriptor include split a block into
> constituent granules, the Armv8-A and SMMUv3 architectures require
> a break-before-make procedure. But in the function arm_lpae_split_blk_unmap,
> it changes a block descriptor to an equivalent span of page translations
> directly. Is it appropriate to do so?

Break-before-make doesn't really work for the SMMU because faults are
generally fatal.

Are you seeing problems in practice with this code?

Will
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  reply	other threads:[~2020-11-03  9:11 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03  3:00 Some questions about arm_lpae_install_table Kunkun Jiang
2020-11-03  9:11 ` Will Deacon [this message]
2020-11-03 10:21   ` Robin Murphy
2020-11-04  7:17     ` Kunkun Jiang
2020-11-04 11:15       ` Robin Murphy

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