From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0670C433FE for ; Fri, 27 May 2022 21:39:02 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 5FE9D6F4BA; Fri, 27 May 2022 21:39:02 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ffo--MuReD_g; Fri, 27 May 2022 21:39:01 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [IPv6:2605:bc80:3010:104::8cd3:938]) by smtp3.osuosl.org (Postfix) with ESMTPS id 449E56F4BC; Fri, 27 May 2022 21:39:01 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id 76ECFC0086; Fri, 27 May 2022 21:39:00 +0000 (UTC) Received: from smtp3.osuosl.org (smtp3.osuosl.org [IPv6:2605:bc80:3010::136]) by lists.linuxfoundation.org (Postfix) with ESMTP id 2DCB2C002D for ; Fri, 27 May 2022 21:38:58 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 07F3A6F4BA for ; Fri, 27 May 2022 21:38:58 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id E9PgF7yswGGg for ; Fri, 27 May 2022 21:38:56 +0000 (UTC) X-Greylist: from auto-whitelisted by SQLgrey-1.8.0 Received: from relay04.th.seeweb.it (relay04.th.seeweb.it [5.144.164.165]) by smtp3.osuosl.org (Postfix) with ESMTPS id 215BC6F4B1 for ; Fri, 27 May 2022 21:38:56 +0000 (UTC) Received: from localhost.localdomain (abxh119.neoplus.adsl.tpnet.pl [83.9.1.119]) by m-r1.th.seeweb.it (Postfix) with ESMTPA id 05FF8206D5; Fri, 27 May 2022 23:29:43 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org Subject: [PATCH 6/6] iommu/qcom: Add support for QCIOMMUv2 and QCIOMMU-500 secured contexts Date: Fri, 27 May 2022 23:29:01 +0200 Message-Id: <20220527212901.29268-7-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220527212901.29268-1-konrad.dybcio@somainline.org> References: <20220527212901.29268-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Cc: devicetree@vger.kernel.org, Robin Murphy , Konrad Dybcio , linux-kernel@vger.kernel.org, jamipkettunen@somainline.org, Rob Herring , Andy Gross , martin.botka@somainline.org, Krzysztof Kozlowski , angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, Will Deacon X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" From: AngeloGioacchino Del Regno This IOMMU is yet another Qualcomm variant of known IOMMUs, found in Family-B SoCs, such as MSM8956, MSM8976, MSM8953, MSM8917 and others, and that firmware perfectly adheres to this driver logic. This time, though, the catch is that the secure contexts are also secured, meaning that these are programmed by the bootloader or TZ and their "interesting" registers are locked out, so the hypervisor disallows touching them from the non-secure world: in this case the OS is supposed to blindly trust the secure configuration of these contexts and just use them "as they are". For this reason, it is necessary to distinguish between the v1 and 500/v2 secure contexts in this driver in order to adhere to this specification. To do this, add a new DT compatible, named "qcom,msm-iommu-v2-sec" that will trigger the new behavior. For the sake of completeness, also add a "qcom,msm-iommu-v2-ns" so that the human eye gets pleased with it when reading the contexts in the final SoC DT. Of course, the latter is just cosmetic. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Marijn Suijten Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/iommu/qcom,iommu.txt | 2 ++ drivers/iommu/arm/arm-smmu/qcom_iommu.c | 18 ++++++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt index 72ae0595efff..861c0cd9c512 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt @@ -36,6 +36,8 @@ to non-secure vs secure interrupt line. - compatible : Should be one of: - "qcom,msm-iommu-v1-ns" : non-secure context bank - "qcom,msm-iommu-v1-sec" : secure context bank + - "qcom,msm-iommu-v2-ns" : non-secure QSMMUv2/QSMMU500 context bank + - "qcom,msm-iommu-v2-sec" : secure QSMMUv2/QSMMU500 context bank - reg : Base address and size of context bank within the iommu - interrupts : The context fault irq. diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 4fefbab15b71..aa7359ae34a9 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -60,6 +60,7 @@ struct qcom_iommu_ctx { struct device *dev; void __iomem *base; bool secure_init; + bool secured_ctx; u8 asid; /* asid and ctx bank # are 1:1 */ struct iommu_domain *domain; }; @@ -309,6 +310,12 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, ctx->secure_init = true; } + /* Secured QSMMU-500/QSMMU-v2 contexts cannot be programmed */ + if (ctx->secured_ctx) { + ctx->domain = domain; + break; + } + qcom_iommu_reset_ctx(ctx); @@ -751,10 +758,14 @@ static int qcom_iommu_ctx_probe(struct platform_device *pdev) if (irq < 0) return -ENODEV; + if (of_device_is_compatible(dev->of_node, "qcom,msm-iommu-v2-sec")) + ctx->secured_ctx = true; + /* clear IRQs before registering fault handler, just in case the * boot-loader left us a surprise: */ - iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR)); + if (!ctx->secured_ctx) + iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR)); ret = devm_request_irq(dev, irq, qcom_iommu_fault, @@ -796,6 +807,8 @@ static int qcom_iommu_ctx_remove(struct platform_device *pdev) static const struct of_device_id ctx_of_match[] = { { .compatible = "qcom,msm-iommu-v1-ns" }, { .compatible = "qcom,msm-iommu-v1-sec" }, + { .compatible = "qcom,msm-iommu-v2-ns" }, + { .compatible = "qcom,msm-iommu-v2-sec" }, { /* sentinel */ } }; @@ -813,7 +826,8 @@ static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu) struct device_node *child; for_each_child_of_node(qcom_iommu->dev->of_node, child) - if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) + if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec") || + of_device_is_compatible(child, "qcom,msm-iommu-v2-sec")) return true; return false; -- 2.36.1 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu