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Tue, 13 Sep 2022 08:24:54 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 13 Sep 2022 01:24:54 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Tue, 13 Sep 2022 01:24:52 -0700 From: Nicolin Chen To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH 0/5] iommu: Define EINVAL as device/domain incompatibility Date: Tue, 13 Sep 2022 01:24:43 -0700 Message-ID: <20220913082448.31120-1-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT068:EE_|SN7PR12MB6861:EE_ X-MS-Office365-Filtering-Correlation-Id: 25a05856-dc4e-4e42-ff64-08da95617009 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2022 08:24:54.8696 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25a05856-dc4e-4e42-ff64-08da95617009 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6861 This series is to replace the previous EMEDIUMTYPE patch in a VFIO series: https://lore.kernel.org/kvm/Yxnt9uQTmbqul5lf@8bytes.org/ The purpose is to regulate all existing ->attach_dev callback functions to use EINVAL exclusively for an incompatibility error between a device and a domain. This allows VFIO and IOMMUFD to detect such a soft error, and then try a different domain with the same device. Among the five patches, the first two are preparatory changes. And then a patch to update kdocs and another two patches for the enforcement efforts. Although it might be ideal to merge the previous VFIO series together with this series, given the number of new changes, the review in the IOMMU list might need a couple of rounds to finalize. Also, considering that v6.0 is at rc5 now, perhaps we could merge this IOMMU series and the VFIO one in different cycles to avoid merge conflicts. If there's less concern for it, I can respin the finalized version of this series with the previous VFIO one to merge together into the VFIO tree. This series is also available on Github: https://github.com/nicolinc/iommufd/commits/iommu_attach_dev Thanks! Nicolin Chen (5): iommu/msm: Add missing __disable_clocks calls iommu/amd: Drop unnecessary checks in amd_iommu_attach_device() iommu: Add return errno rules to ->attach_dev ops iommu: Regulate errno in ->attach_dev callback functions iommu: Use EINVAL for incompatible device/domain in ->attach_dev drivers/iommu/amd/iommu.c | 12 ++---------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 13 ++----------- drivers/iommu/arm/arm-smmu/arm-smmu.c | 7 ++----- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 9 ++------- drivers/iommu/fsl_pamu.c | 6 +++--- drivers/iommu/fsl_pamu_domain.c | 4 ++-- drivers/iommu/intel/iommu.c | 10 +++------- drivers/iommu/intel/pasid.c | 2 +- drivers/iommu/ipmmu-vmsa.c | 4 +--- drivers/iommu/msm_iommu.c | 2 ++ drivers/iommu/mtk_iommu.c | 9 ++++++--- drivers/iommu/omap-iommu.c | 6 +++--- drivers/iommu/rockchip-iommu.c | 4 +++- drivers/iommu/sprd-iommu.c | 4 +--- drivers/iommu/tegra-gart.c | 2 +- drivers/iommu/tegra-smmu.c | 2 +- drivers/iommu/virtio-iommu.c | 6 +++--- include/linux/iommu.h | 11 +++++++++++ 18 files changed, 49 insertions(+), 64 deletions(-) -- 2.17.1