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Fri, 9 Jun 2023 05:18:31 -0500 From: Vasant Hegde To: , CC: , , Vasant Hegde Subject: [PATCH 2/2] iommu/amd: Handle PPR log overflow Date: Fri, 9 Jun 2023 10:17:46 +0000 Message-ID: <20230609101746.6412-3-vasant.hegde@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230609101746.6412-1-vasant.hegde@amd.com> References: <20230609101746.6412-1-vasant.hegde@amd.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT078:EE_|DM4PR12MB6662:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b819aa4-c021-4717-b41c-08db68d2e1bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SO6kC14GmKBtVzJQoz7nI2mk/E7NFng9vpWTi1PhMrZl8vlyLCHg96sYVutOuS/85ATdQ/jDJXtwrgt+utRMrkl2A57CcjbHZxpzDpKj0al/TrCuixrWY6eFg7+jSXTMko4b8ZeAjq05PYt4SUB3nDPxFCtjmR2bPPvnGFGuyMxtdR993lq4XpSnB0PE5YmA8jecVfsqm94g5MhWKfM5iHOm1aqcoMMirKM8R91yzp6+PTDk55npgLn75mJGYN34SE3u9avrUKkzd9uNT8Nvurl5NpLqyQ63krI1tAe+p1Fm6yxfTPExxzxtAGXgkzJZteVedVEp3MeKrPlDOdknT+WTTMdNJsid2ZElhFPFolmyccX2h/iP4yh3FOubDjXwFVz57WcOk5GUf+b0t4r80Q5kNUgwEQTPI3zvMlqChAk+2VVh3hZLYzEAUcM7NsOYF/5G6EC+0fR+QJPR2J59HTcWXYlj3XVM3R7L34DtXiSXyzDtuXRfKqKeQGXWkxjVagSHz6vbx4d7FgFEfFDsWJtUb2kZag4hcoNjn9E/QCW1OymxObrULFSfXUSzbISHqOXIUu6zylapjyMSOXBPpF4jEJN7OX+NNUgatLnJ1P6RYa9LMMk16oqMiWdqPPjNgg/X6TIai23ZwmJOSD9UhkI1kKpB3Hhd4gK61pCftsEq16tG1PWL42hR4m6brkeS7IAPyJag+pB7k8dyOtAMttuBRXpX5s3+jDSrEGOq+lwFAU4d6O8kwyZ24Zbcm9Bt79/nEePIkqFGFvGWuneFjA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(39860400002)(376002)(396003)(136003)(451199021)(46966006)(36840700001)(40470700004)(26005)(1076003)(16526019)(336012)(2616005)(426003)(966005)(83380400001)(47076005)(36860700001)(186003)(82310400005)(6666004)(70206006)(82740400003)(2906002)(70586007)(81166007)(356005)(7696005)(40460700003)(44832011)(8676002)(8936002)(5660300002)(110136005)(54906003)(36756003)(478600001)(86362001)(41300700001)(40480700001)(316002)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2023 10:18:34.1871 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b819aa4-c021-4717-b41c-08db68d2e1bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT078.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6662 Some ATS-capable peripherals can issue requests to the processor to service peripheral page requests using PCIe PRI (the Page Request Interface). IOMMU supports PRI using PPR log buffer. IOMMU writes PRI request to PPR log buffer and sends PPR interrupt to host. When there is no space in the PPR log buffer (PPR log overflow) it will set PprOverflow bit in 'MMIO Offset 2020h IOMMU Status Register'. When this happens PPR log needs to be restarted as specified in IOMMU spec [1] section 2.6.2. When handling the event it just resumes the PPR log without resizing (similar to the way event and GA log overflow is handled). Failing to handle PPR overflow means device may not work properly as IOMMU stops processing new PPR events from device. [1] https://www.amd.com/system/files/TechDocs/48882_3.07_PUB.pdf Signed-off-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/amd_iommu_types.h | 2 ++ drivers/iommu/amd/init.c | 11 +++++++++++ drivers/iommu/amd/iommu.c | 9 ++++++++- 4 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 317d5c26c614..156f57b4f78c 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -16,6 +16,7 @@ irqreturn_t amd_iommu_int_handler(int irq, void *data); void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid); void amd_iommu_restart_event_logging(struct amd_iommu *iommu); void amd_iommu_restart_ga_log(struct amd_iommu *iommu); +void amd_iommu_restart_ppr_log(struct amd_iommu *iommu); void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid); #ifdef CONFIG_AMD_IOMMU_DEBUGFS diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 318b84cf47f6..a993e1bdb70b 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -124,7 +124,9 @@ #define MMIO_STATUS_EVT_INT_MASK BIT(1) #define MMIO_STATUS_COM_WAIT_INT_MASK BIT(2) #define MMIO_STATUS_EVT_RUN_MASK BIT(3) +#define MMIO_STATUS_PPR_OVERFLOW_MASK BIT(5) #define MMIO_STATUS_PPR_INT_MASK BIT(6) +#define MMIO_STATUS_PPR_RUN_MASK BIT(7) #define MMIO_STATUS_GALOG_RUN_MASK BIT(8) #define MMIO_STATUS_GALOG_OVERFLOW_MASK BIT(9) #define MMIO_STATUS_GALOG_INT_MASK BIT(10) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 3c21e9333899..9908cd4f1c31 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -795,6 +795,17 @@ void amd_iommu_restart_ga_log(struct amd_iommu *iommu) MMIO_STATUS_GALOG_OVERFLOW_MASK); } +/* + * This function restarts ppr logging in case the IOMMU experienced + * PPR log overflow. + */ +void amd_iommu_restart_ppr_log(struct amd_iommu *iommu) +{ + amd_iommu_restart_log(iommu, "PPR", CONTROL_PPRINT_EN, + CONTROL_PPRLOG_EN, MMIO_STATUS_PPR_RUN_MASK, + MMIO_STATUS_PPR_OVERFLOW_MASK); +} + /* * This function resets the command buffer if the IOMMU stopped fetching * commands from it. diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index a29548d98b6a..3c179d548ecd 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -844,6 +844,7 @@ amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { } #define AMD_IOMMU_INT_MASK \ (MMIO_STATUS_EVT_OVERFLOW_MASK | \ MMIO_STATUS_EVT_INT_MASK | \ + MMIO_STATUS_PPR_OVERFLOW_MASK | \ MMIO_STATUS_PPR_INT_MASK | \ MMIO_STATUS_GALOG_OVERFLOW_MASK | \ MMIO_STATUS_GALOG_INT_MASK) @@ -863,11 +864,17 @@ irqreturn_t amd_iommu_int_thread(int irq, void *data) iommu_poll_events(iommu); } - if (status & MMIO_STATUS_PPR_INT_MASK) { + if (status & (MMIO_STATUS_PPR_INT_MASK | + MMIO_STATUS_PPR_OVERFLOW_MASK)) { pr_devel("Processing IOMMU PPR Log\n"); iommu_poll_ppr_log(iommu); } + if (status & MMIO_STATUS_PPR_OVERFLOW_MASK) { + pr_info_ratelimited("IOMMU PPR log overflow\n"); + amd_iommu_restart_ppr_log(iommu); + } + #ifdef CONFIG_IRQ_REMAP if (status & (MMIO_STATUS_GALOG_INT_MASK | MMIO_STATUS_GALOG_OVERFLOW_MASK)) { -- 2.31.1