From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D04DE14A86 for ; Wed, 19 Jul 2023 15:37:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4E060C433C8; Wed, 19 Jul 2023 15:37:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689781065; bh=8vE1ot6XzFQ4H6sBrVB9YMCDiYUQPwwfTpKgGcHZcng=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=vQ6SfMBZY0QHME2fvrVuvDrOXOy58YBPTNc7A5lnuITNetabLNPEaeOM2paMu+SpH 5fMLvaTesCUu8r4E9urcNhjlR7E4aivQOfNQzRn1o1jn817gmOMeIa1MvStD1DfCzt fBFry24AMlETBkSftX5RdTBdnz8W/t8XEOKOYCPXLw0CeV8oZa6Ui1Tt9nV996Qvya kzyPIyx4lWfbOSz2EEqnGaTgNKe3K74mHGHwnrZubbMdJulY533/o/Zbzbz3kWDje2 cGmv3z9PZMUxUmLBOk+COJeg3K9jHOolKstg/tJLUNv/I7e0ofES8Q8fbd2oUDIzwL zYMgGTrtzPBBw== Date: Wed, 19 Jul 2023 21:07:27 +0530 From: Manivannan Sadhasivam To: Parikshit Pareek Cc: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , Marijn Suijten , Adam Skladowski , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, "linux-kernel @ vger . kernel . org Prasanna Kumar" , Shazad Hussain Subject: Re: [PATCH 0/3] arm64: dts: qcom: sa8775p: Add interconnect to SMMU Message-ID: <20230719153727.GD9312@thinkpad> References: <20230609054141.18938-1-quic_ppareek@quicinc.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230609054141.18938-1-quic_ppareek@quicinc.com> On Fri, Jun 09, 2023 at 11:11:39AM +0530, Parikshit Pareek wrote: > Some qcom SoCs have SMMUs, which need the interconnect bandwidth to be > This series introduce the due support for associated interconnect, and > setting of the due interconnect-bandwidth. Setting due interconnect > bandwidth is needed to avoid the issues like [1], caused by not having > due clock votes(indirectly dependent upon interconnect bandwidth). > As discussed offline, once you enable the PCIe RC driver which votes for this interconnect path (pcie-mem) like other platforms [1], then you do not need this series. This interconnect path belongs to the PCIe RC controller. So it is the responsibility of the PCIe RC driver to vote for this path and that's what the driver is already doing. - Mani [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/qcom/sc8280xp.dtsi#n1767 > Parikshit Pareek (3): > dt-bindings: arm-smmu: Add interconnect for qcom SMMUs > arm64: dts: qcom: sa8775p: Add interconnect to PCIe SMMU > iommu/arm-smmu-qcom: Add support for the interconnect > > .../devicetree/bindings/iommu/arm,smmu.yaml | 22 +++++++++++++++++++ > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++++ > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 16 ++++++++++++++ > 3 files changed, 42 insertions(+) > > -- > 2.17.1 > -- மணிவண்ணன் சதாசிவம்