From: Vasant Hegde <vasant.hegde@amd.com>
To: <iommu@lists.linux.dev>, <joro@8bytes.org>
Cc: <suravee.suthikulpanit@amd.com>, <wei.huang2@amd.com>,
<jsnitsel@redhat.com>, <jgg@ziepe.ca>,
Vasant Hegde <vasant.hegde@amd.com>,
Jason Gunthorpe <jgg@nvidia.com>
Subject: [PATCH v8 02/15] iommu/amd: Introduce per device DTE update function
Date: Thu, 18 Apr 2024 10:33:47 +0000 [thread overview]
Message-ID: <20240418103400.6229-3-vasant.hegde@amd.com> (raw)
In-Reply-To: <20240418103400.6229-1-vasant.hegde@amd.com>
Consolidate per device update and flush logic into separate function.
Also make it as global function as it will be used in subsequent series
to update the DTE.
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
---
drivers/iommu/amd/amd_iommu.h | 1 +
drivers/iommu/amd/iommu.c | 26 ++++++++++++++++++--------
2 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index d77660551f2a..98aa3ce8473f 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -56,6 +56,7 @@ int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid);
void amd_iommu_flush_all_caches(struct amd_iommu *iommu);
void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
void amd_iommu_domain_update(struct protection_domain *domain);
+void amd_iommu_dev_update_dte(struct iommu_dev_data *dev_data, bool set);
void amd_iommu_domain_flush_complete(struct protection_domain *domain);
void amd_iommu_domain_flush_pages(struct protection_domain *domain,
u64 address, size_t size);
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index e692217fcb28..394623abbaa4 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2002,6 +2002,21 @@ static void clear_dte_entry(struct amd_iommu *iommu, u16 devid)
amd_iommu_apply_erratum_63(iommu, devid);
}
+/* Update and flush DTE for the given device */
+void amd_iommu_dev_update_dte(struct iommu_dev_data *dev_data, bool set)
+{
+ struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev);
+
+ if (set)
+ set_dte_entry(iommu, dev_data);
+ else
+ clear_dte_entry(iommu, dev_data->devid);
+
+ clone_aliases(iommu, dev_data->dev);
+ device_flush_dte(dev_data);
+ iommu_completion_wait(iommu);
+}
+
static int do_attach(struct iommu_dev_data *dev_data,
struct protection_domain *domain)
{
@@ -2036,10 +2051,7 @@ static int do_attach(struct iommu_dev_data *dev_data,
}
/* Update device table */
- set_dte_entry(iommu, dev_data);
- clone_aliases(iommu, dev_data->dev);
-
- device_flush_dte(dev_data);
+ amd_iommu_dev_update_dte(dev_data, true);
return ret;
}
@@ -2058,11 +2070,9 @@ static void do_detach(struct iommu_dev_data *dev_data)
/* Update data structures */
dev_data->domain = NULL;
list_del(&dev_data->list);
- clear_dte_entry(iommu, dev_data->devid);
- clone_aliases(iommu, dev_data->dev);
- /* Flush the DTE entry */
- device_flush_dte(dev_data);
+ /* Clear DTE and flush the entry */
+ amd_iommu_dev_update_dte(dev_data, false);
/* Flush IOTLB and wait for the flushes to finish */
amd_iommu_domain_flush_all(domain);
--
2.31.1
next prev parent reply other threads:[~2024-04-18 10:34 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-18 10:33 [PATCH v8 00/15] iommu/amd: SVA Support (Part 4) - SVA and IOPF Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 01/15] iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported() Vasant Hegde
2024-04-18 10:33 ` Vasant Hegde [this message]
2024-04-18 10:33 ` [PATCH v8 03/15] iommu/amd: Add support for enabling/disabling IOMMU features Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 04/15] iommu/amd: Move PPR-related functions into ppr.c Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 05/15] iommu/amd: Fix PPR interrupt processing logic Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 06/15] iommu/amd: Introduce iommu_dev_data.max_pasids Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 07/15] iommu/amd: Setup GCR3 table in advance if domain is SVA capable Vasant Hegde
2024-05-02 13:16 ` Klara Modin
2024-05-03 10:26 ` Joerg Roedel
2024-05-06 6:42 ` Vasant Hegde
2024-05-06 7:31 ` Vasant Hegde
2024-05-06 7:47 ` Klara Modin
2024-05-06 8:15 ` Joerg Roedel
2024-05-06 8:25 ` Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 08/15] iommu/amd: Enable PCI features based on attached domain capability Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 09/15] iommu/amd: Define per-IOMMU iopf_queue Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 10/15] iommu/amd: Add support for page response Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 11/15] iommu/amd: Add IO page fault notifier handler Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 12/15] iommu/amd: Add support for enable/disable IOPF Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 13/15] iommu/amd: Initial SVA support for AMD IOMMU Vasant Hegde
2024-04-18 10:33 ` [PATCH v8 14/15] iommu: Add ops->domain_alloc_sva() Vasant Hegde
2024-04-18 10:34 ` [PATCH v8 15/15] iommu/amd: Add SVA domain support Vasant Hegde
2024-04-26 10:57 ` [PATCH v8 00/15] iommu/amd: SVA Support (Part 4) - SVA and IOPF Joerg Roedel
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